AHB Interview Questions

Every transfer has an address phase of one cycle and a data phase of one or more cycles. The next transfer's address phase happens during the current transfer's data phase. With no wait states, the bus finishes one transfer per cycle. Each transfer still takes two cycles from address to data. So write data trails its address by a cycle. At most two transfers are on the bus at once: one in address, one in data.

It gains a full cycle between seeing the address and having to produce or take the data. That is time to decode and start a memory access. Meanwhile the bus still completes one transfer per cycle. Without the overlap, a bus must halve its throughput. Or it must force every subordinate to answer in the same cycle it sees the address.

The bus is pipelined. When a subordinate starts an ERROR, the next transfer's address phase is already on the bus. The first cycle (HRESP high, HREADYOUT low) holds that address phase and warns the manager. In the second cycle (HRESP high, HREADYOUT high), the manager can drive IDLE. That cancels the next transfer before anyone takes it. Wait states before the error carry HRESP low.

Beat 3's address phase was on the bus during the first error cycle. The manager turns it into IDLE in the second cycle. So no subordinate ever takes it, because it is never accepted as NONSEQ or SEQ with HREADY high. The manager need not rebuild the remaining beats later. During that waited cycle, it may also change the address, which the normal hold rule forbids.

It is legal: cancelling the rest of the burst is allowed, not required. So the checker must accept both IDLE in the second error cycle and a burst that carries on. The subordinate answers the later beats normally. A checker that flags the continued burst reports a false failure on a legal manager.

Check both directions. A first ERROR cycle (HRESP high, HREADYOUT low) must be followed by a second (HRESP high, HREADYOUT high). And a second cycle must be preceded by a first. The one-cycle error passes the first property vacuously: there is no first cycle to trigger it. It fails only the second, so a checker with just one of them misses it.

AHB has one response bit, so a decode error is ERROR from the default subordinate for unmapped NONSEQ or SEQ transfers. APB's PSLVERR counts only in the single completion cycle, and needs no second cycle because APB is not pipelined. AXI separates SLVERR (the end point refused) from DECERR (no end point). It reports per read beat and once per write, and never shortens a burst. Bridges map PSLVERR to HRESP or to RRESP/BRESP.

The wait states stretch the data phase of the read. They also stretch the address phase of the next transfer, which stays on the wires until HREADY is high. Each subordinate drives HREADYOUT for its own data phase. The multiplexor picks the HREADYOUT of the subordinate whose data phase is active. It sends that as HREADY to the manager and to every subordinate. A subordinate takes an address phase only at an edge where its HSEL and HREADY are both high.

The data phase in front may belong to another subordinate. HREADY says when that data phase ends. Only then does the address phase on the wires count as accepted. A subordinate that samples on HSEL alone may act too early. The address phase may still change, such as an IDLE becoming NONSEQ, or the manager may cancel it after an ERROR.

While the data phase in front is in a wait state, HSEL and the address can already point at this subordinate. It then takes a transfer the bus has not accepted yet. If the manager changes IDLE to NONSEQ, or cancels after an ERROR, the subordinate acts on the wrong transfer. Across a long wait it can even take one transfer twice.

Normally no, with three exceptions. IDLE may become NONSEQ, and in a fixed-length burst BUSY may become SEQ. In an undefined-length INCR burst, BUSY may become anything, and IDLE or NONSEQ ends the burst. After any such change, HTRANS is held until HREADY is high. The address may change only for IDLE, or after an ERROR has started.

Wait states stall the whole AHB interface. So the worst-case latency of every manager depends on the slowest subordinate it can reach. A known maximum per subordinate lets you compute that latency. Check it with a watchdog per subordinate, set to its documented bound. Add performance tests that hit the worst case and, for small blocks, a bounded-response property in formal.

An address phase is taken at an edge where HREADY is high and HTRANS is NONSEQ or SEQ. On a subordinate port, HSEL must be high too. Its data phase ends at the next edge where HREADY is high, and HWDATA, HRDATA and HRESP belong to it there. Monitors often log at the address phase and pair the wrong data. Others ignore HREADY and log a waiting transfer several times, or read HRESP as final in the first ERROR cycle.

AHB has one address and control path, with at most one transfer in address and one in data. Transfers complete in order, and a wait state stalls whatever is behind it. AXI has independent channels and IDs, so a manager can issue many requests without waiting. Responses with different IDs may return out of order. AHB wins on area and simplicity for a single manager with modest latency, such as a microcontroller memory bus.

The register block takes address phases without checking HTRANS. IDLE and BUSY must get a zero-wait OKAY and be ignored. But the manager may leave the last write's HADDR and HWRITE on the bus. A block that decodes only HSEL, HWRITE and HADDR treats each IDLE as another write. It stores whatever HWDATA holds. Take a write only when HSEL and HREADY are high and HTRANS is NONSEQ or SEQ.

IDLE means the manager wants no transfer. BUSY means a burst is continuing, but its next beat is not ready yet. Its address and control already describe that next beat. The subordinate answers both the same way: a zero-wait OKAY and no action.

It keeps the burst continuous. When the manager is ready, it turns BUSY into SEQ with the same address. So the subordinate can keep prefetching. Only an undefined-length INCR may end after BUSY, followed by IDLE or NONSEQ. Fixed-length INCR4/8/16 and WRAP4/8/16 must end with a SEQ beat, and BUSY may never follow a SINGLE.

No. Every wire was legal, because the manager may leave the address on the bus during IDLE. Only the data shows the bug. A scoreboard or register model that reads back after idle gaps catches it. Assertions own the wire rules (holds, two-cycle ERROR, SEQ addresses, 1 KB crossings). The scoreboard owns subordinate behaviour (data taken in the wrong phase, lanes HSIZE did not select, actions on IDLE).

These bugs need two subordinates at once. A mux select on the wrong phase shows only on back-to-back accesses to different subordinates. A HREADY fan-in that forwards the wrong HREADYOUT shows only when one subordinate waits while another is addressed. A region off-by-one shows only at a 1 KB edge, and a one-cycle default-subordinate error only on unmapped accesses. Expose them with back-to-back cross-subordinate traffic, random waits and address sweeps at every region boundary.

The decoder turns HADDR into one HSELx during the address phase. The multiplexor returns HRDATA, HRESP and HREADYOUT from the subordinate whose data phase is in progress. So its select is the decoder output, registered at every edge where HREADY is high. The live decoder output already names the next transfer. A default subordinate fills the holes in the map, so nothing hangs. It gives a zero-wait OKAY for IDLE and BUSY, and a two-cycle ERROR for NONSEQ and SEQ.

HBURST gives SINGLE, undefined-length INCR, and fixed INCR4/8/16 and WRAP4/8/16. The number counts beats, not bytes. A wrapping burst wraps inside a window of beats times size. So a WRAP4 of words from 0x34 visits 0x34, 0x38, 0x3C, 0x30. An incrementing burst must not cross a 1 KB boundary, because subordinate regions are at least 1 KB and 1 KB aligned. Every beat is aligned to its size.

Subordinate regions are at least 1 KB, and they start and end on 1 KB boundaries. So a burst that stays inside one 1 KB block never changes subordinate mid-burst. Subordinates can then treat SEQ beats as a continuation without decoding again. AXI applies the same idea with a 4 KB boundary. A wrapping burst stays inside its own aligned window, which on usual bus widths is far smaller than 1 KB.

The beats are 0x3F8, 0x3FC, 0x400 and 0x404. The third beat starts the next 1 KB block, which may belong to another subordinate. That subordinate sees a SEQ beat with no NONSEQ before it. The manager must split the request: two beats, then a new NONSEQ at 0x400.

The window is beats times size, aligned to its own size. Add the size to the address. For a wrapping burst, if that reaches the end of the window, go back to the window's base. The run reproduces the specification's WRAP4, INCR4, WRAP8 and halfword INCR8 examples. The classic bug is a window sized for the old burst length, which turns WRAP8 back at 16 bytes.

A manager may not end a fixed-length burst on its own, but two things can end it. After an ERROR, the manager may cancel the remaining beats. A multi-layer interconnect may also cut a burst to serve another manager. An INCR burst also ends whenever BUSY is followed by IDLE or NONSEQ. Subordinates must work correctly when a burst never completes, for example by dropping prefetched data.

An interconnect adds arbitration and routing, because the AHB interface itself stays single-manager. It stalls a waiting manager by holding its HREADY low. A multi-layer interconnect may cut a burst short to serve another manager, so subordinates must cope with unfinished bursts. Locked sequences need HMASTLOCK, and exclusives need HMASTER to tell managers apart. The plan adds per-port checkers, routing scoreboards, fairness coverage and terminated-burst coverage.