Interview Question · Concept
PSLVERR and What It Promises
The Question
The interviewer asks
When is PSLVERR valid? And if a write gets PSLVERR, was the register written or not?
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Reveal the Model Answer
PSLVERR counts only in the last cycle of the transfer, where PSEL, PENABLE and PREADY are all high. Elsewhere it is ignored, and driving it low there is only a recommendation. It says the transfer failed, not what happened inside. A failed write may or may not have changed the register. A failed read may return data that the requester still uses. PSLVERR is optional; without it the requester's input is tied low.
p0.waits = 1: cycle 0 is edge 3. The first write ends at edge 5, the second at edge 8.The pill is the answer the requester takes: OKAY or ERROR, only at the end of a transfer.
- Cycle 0
Setup of a write to CTRL at 0x100.
- Cycle 1
Access, but
preadyis 0: a wait state.pslverrmeans nothing here. - Cycle 2
preadyis 1 andpslverris 0. The write completes OKAY and CTRL takes the data. - Cycle 3
Setup of a write to STATUS at 0x104, a read-only register.
- Cycle 4
Another wait state. The completer knows the answer already and keeps
pslverrlow, as recommended. - Cycle 5
The last cycle:
preadyandpslverrtogether. The requester records the error.
A requester samples PSLVERR at the same edge it samples PREADY high, and at no other edge.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer states that PSLVERR counts only in the completion cycle. It also says a failed write may still have changed the register.
What Interviewers Listen For (Mid-Level)
A good mid-level answer adds that read data with an error need not be zero. So an error does not hide the value. It knows PSLVERR came with APB3. It says a checker may at most note PSLVERR outside the completion cycle, never fail on it.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompareScale It
- PSLVERR and What It Promises
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WhyWhy an APB Error Promises so LittleL2 Mid-Level
Why doesn't the APB specification guarantee that an errored write left the register alone?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Completers differ, and the specification keeps them cheap. Some decide the error only after part of the access has taken effect; others refuse cleanly. Forcing "no side effect on error" would add buffering to every peripheral. So the error reports failure only. The register's behaviour on error belongs in the peripheral's documentation and its register model.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says the effect of a failed write depends on the peripheral. That effect must be documented and modelled for each register.
What Interviewers Listen For (Senior)
A good senior answer puts that policy into the register model or scoreboard. It skips the prediction on error, or follows the documented rule. It also puts the policy into firmware guidance.
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What IfA Register Model That Predicts an Errored WriteL2 Mid-Level
What if your register model still predicts the write after PSLVERR comes back?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Then the mirror holds a value the register may not have. The next read check fails on a correct design, or passes on a wrong one. The adapter should return
UVM_NOT_OK, so the model skips predicting that access. Then read the register back to learn what the peripheral really did.Self-Check
Tick each key point you covered in your answer.
Spec Misquote
"An errored write never changes the register."
The spec allows either result. Only the peripheral documentation or a readback tells you which one you have.
Source AMBA APB Protocol Specification IHI 0024E §3.4 Error response
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ComparePSLVERR Through an AXI BridgeL2 Mid-LevelL3 Senior
How does PSLVERR reach an AXI manager through a bridge? A 4-beat AXI write becomes four APB transfers and the second gets PSLVERR. What does the manager see?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The bridge maps PSLVERR to SLVERR, in the RRESP of the failing beat for a read and in BRESP for a write. A write has one completion response for the whole transaction. So the bridge must merge four APB results into one BRESP. Reporting SLVERR if any beat failed is the usual choice. The remaining beats still run: AXI never shortens a burst, and every read beat is returned whatever its response.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer knows AXI reads report a response per beat but writes report once. So the bridge must merge the four APB results into one.
What Interviewers Listen For (Senior)
A good senior answer calls the merge rule a design decision that must be documented. It asks whether later beats should still be written after a failure. It checks that the read side still returns every beat after an error.
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Scale ItSigning off APB Error HandlingL2 Mid-LevelL3 Senior
What would you check and cover before you sign off error handling on an APB peripheral?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Check that each refused access errors: a write to read-only, an unmapped offset, or a wrong size or protection. Check that PSLVERR is read only at completion, and that register state after a failed write matches the documented policy. Cover read and write, crossed with error or not, crossed with zero, one and many wait states. Also cover an error followed straight by a good transfer to the same completer. Then check the error reaches software through the bridge.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer lists the causes of an error. It crosses read or write, error or not, and the number of wait states in coverage.
What Interviewers Listen For (Senior)
A good senior answer adds the path to software, through BRESP or RRESP and an interrupt or status bit. It also tests a good transfer right after an error. Its exit rule: every documented refusal is hit in each wait class.
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Prove ItSolve P3.4.1: The Error on the Wrong CycleSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Spec Misquote
A write that gets PSLVERR leaves the register unchanged.
The specification leaves it to each peripheral. An errored transfer might or might not have changed the peripheral's state. Software must read back, or follow the peripheral's documentation.
Source AMBA APB Protocol Specification IHI 0024E §3.4 Error response
Misconception
PSLVERR high in any other cycle is a protocol error the checker must flag.
Driving PSLVERR low outside the completion cycle is recommended, not required. A checker that fails it rejects a legal completer.
Source AMBA APB Protocol Specification IHI 0024E §3.4 Error response
Missed Corner
Sample PSLVERR when PENABLE rises, together with the transfer's start.
With a wait state the first ACCESS edge is not the completion edge. The sampler below reports OKAY for a write the completer refused at completion.
Run It
FAIL first-access sampler: pslverr=0 PASS completion sampler: pslverr=1