Interview Question · Code Reading

Is the Hold Rule Enough?

L1 JuniorL2 Mid-Levelhandshakecheckerssva

The interviewer asks

Our handshake checker is one property: valid && !ready |=> valid. It has never fired. Is the interface covered?

systemverilog

hold_rule: assert property (@(posedge clk)
  valid && !ready |=> valid);

Reveal the Model Answer

No. It checks that valid stays high, but not that the payload stays stable during a stall. So a source that swaps data mid-stall passes. It has no reset rule. And "never fired" may mean "never started": if the tests never stall, the antecedent (the left side of |=>) never matches. Add $stable(payload) under the same antecedent, a reset property, and a count of stalled edges.

Two Stalled Offers, One SpoiledOne lane per stalled edge of valid && !ready |=> $stable(data).valid && !ready |=> $stable(data)Measured on Verilator 5.052: one copy of the assertion per lane

attempt startspassfail

Edge 3 · t=25
a1 is offered and stalled at 15 and 25. Each stalled edge starts an attempt; both find a1 still there.
Edge 7 · t=65
b2 is stalled at 55, and at 65 the bus shows b3. The attempt from 55 fails: the sentence said the data holds.
Edge 8 · t=75
The attempt from 65 passes: b3 held until the transfer. A property decides each stalled edge on its own.

Read the lanes as text

stalled @15, from edge 2 (t=15): passes at edge 3 (t=25).
stalled @25, from edge 3 (t=25): passes at edge 4 (t=35).
stalled @55, from edge 6 (t=55): fails at edge 7 (t=65).
stalled @65, from edge 7 (t=65): passes at edge 8 (t=75).

Sampled values, edge 1 to 9: valid 0 1 1 1 0 1 1 1 0; ready 0 0 0 1 0 0 0 1 0; data 00 a1 a1 a1 00 b2 b3 b3 b3.

The program behind the lanes

The lanes come from running this program on Verilator 5.052. Each lane is a separate copy of stable_data that can start only at that lane's edge, so every verdict and its edge are read from that copy's own output.

module tb;
  logic clk = 0;
  always #5 clk = ~clk;                 // rising edges at 5, 15, 25, ...
  logic valid = 0, ready = 0;
  logic [7:0] data = 8'h00;

  stable_data: assert property (@(posedge clk) valid && !ready |=> $stable(data));

  initial begin
    @(negedge clk); valid = 1; data = 8'ha1;   // offer sampled at 15, stalled
    @(negedge clk);                             // still stalled at 25, data held
    @(negedge clk); ready = 1;                  // taken at 35
    @(negedge clk); valid = 0; ready = 0; data = 8'h00;
    @(negedge clk); valid = 1; data = 8'hb2;    // second offer, sampled at 55, stalled
    @(negedge clk); data = 8'hb3;               // changed while waiting: seen at 65
    @(negedge clk); ready = 1;                  // taken at 75
    @(negedge clk); valid = 0; ready = 0;
    @(negedge clk);
    $finish;
  end
endmodule

The stable-data rule fails at the edge where b2 became b3. A valid-only rule passes that same edge.

Self-Check

Tick each key point you covered in your answer.

Key point 1 No. Key point 2 It checks that valid stays high, but not that the payload stays stable during a stall. Key point 3 So a source that swaps data mid-stall passes. Key point 4 It has no reset rule. Key point 5 And "never fired" may mean "never started": if the tests never stall, the antecedent (the left side of |=>) never matches. Key point 6 Add $stable(payload) under the same antecedent, a reset property, and a count of stalled edges.

What Interviewers Listen For (Junior)

A good junior answer adds the missing rule that the payload must stay stable while the beat waits.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyProve ItBreak ItCompareScale It

Is the Hold Rule Enough?
WhyWhy the Payload Must Not ChangeL1 Junior
The sink has not taken the beat yet. Why can't the source update the data while it waits?

Reveal the Model Answer

Because the sink may already have acted on it. For example, an interconnect may have decoded the address and started arbitration. A registered sink also samples whatever is on the wires at the handshake edge. If the payload can change, the beat the sink receives depends on exactly when ready rose. Neither side controls that.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Because the sink may already have acted on it. Key point 2 For example, an interconnect may have decoded the address and started arbitration. Key point 3 A registered sink also samples whatever is on the wires at the handshake edge. Key point 4 If the payload can change, the beat the sink receives depends on exactly when ready rose. Key point 5 Neither side controls that.

What Interviewers Listen For (Junior)
A good junior answer says the receiver may already have acted on the offered value. Changing it would break what the receiver has started.
- Lesson P1.3Handshakes: Request and Acknowledge, Valid and Ready
Break ItA Checker That Never StartedL2 Mid-Level
How do you prove the checker actually checked something?
2:30

You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.

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Reveal the Model Answer

Measure its antecedents. Count the edges where valid && !ready held, per link and per test, or write cover property (valid && !ready). Zero means the rule was vacuous: it passed without checking anything. Then make sure the agents create stalls. Use random ready with long low runs, and stall on the first beat and on a burst's last beat.

Three Beats, Zero Stalls, Five Vacuous PassesThe hold property on a sink that is always ready.valid && !ready |=> validMeasured on Verilator 5.052: one copy of the assertion per lane

attempt startsvacuous success: the antecedent did not match

Edge 2 · t=15
Beat one is taken at 15 with ready already high. valid && !ready is false, so the attempt ends as it starts.
Edge 5 · t=45
Five edges, five open circles. The hold rule was never exercised, and the report says pass.

Read the lanes as text
edge @5, from edge 1 (t=5): succeeds vacuously at edge 1 (t=5).
edge @15, from edge 2 (t=15): succeeds vacuously at edge 2 (t=15).
edge @25, from edge 3 (t=25): succeeds vacuously at edge 3 (t=25).
edge @35, from edge 4 (t=35): succeeds vacuously at edge 4 (t=35).
edge @45, from edge 5 (t=45): succeeds vacuously at edge 5 (t=45).
Sampled values, edge 1 to 6: valid 0 1 1 1 0 0; ready 1 1 1 1 1 1.
The program behind the lanes
The lanes come from running this program on Verilator 5.052. Each lane is a separate copy of hold_valid that can start only at that lane's edge, so every verdict and its edge are read from that copy's own output.
module tb; logic clk = 0; always #5 clk = ~clk; // rising edges at 5, 15, 25, ... logic valid = 0, ready = 1; // the sink is ready at every edge hold_valid: assert property (@(posedge clk) valid && !ready |=> valid); initial begin @(negedge clk); valid = 1; // three beats, taken at 15, 25 and 35 @(negedge clk); @(negedge clk); @(negedge clk); valid = 0; @(negedge clk); @(negedge clk); $finish; end endmodule

A bus checker needs a slow sink in at least one test, or its most important rules are never tried.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Measure its antecedents. Key point 2 Count the edges where valid && !ready held, per link and per test, or write cover property (valid && !ready). Key point 3 Zero means the rule was vacuous: it passed without checking anything. Key point 4 Then make sure the agents create stalls. Key point 5 Use random ready with long low runs, and stall on the first beat and on a burst's last beat.

What Interviewers Listen For (Mid-Level)
A good mid-level answer writes a cover property or a counter for stalled edges. It also changes the sink agent so tests really create stalls.
- Lesson P1.10From the Spec to a Check
- Problem P1.10.1Properties for the Link
Scale ItSigning off Protocol ChecksL3 SeniorL4 Staff
What would you accept as evidence that the protocol checkers on a subsystem are complete?

Reveal the Model Answer

A traceability table that maps each must-rule in the spec to a property. Each property is bound on every instance of the interface. Every antecedent is covered in regression on every instance, and nothing fires at sign-off except reviewed waivers. Where the risk justifies it, cross-check with a commercial VIP or formal on the same rules. A rule nobody wrote cannot fire.

Self-Check
Tick each key point you covered in your answer.
Key point 1 A traceability table that maps each must-rule in the spec to a property. Key point 2 Each property is bound on every instance of the interface. Key point 3 Every antecedent is covered in regression on every instance, and nothing fires at sign-off except reviewed waivers. Key point 4 Where the risk justifies it, cross-check with a commercial VIP or formal on the same rules. Key point 5 A rule nobody wrote cannot fire.

What Interviewers Listen For (Senior)
A good senior answer asks for a table that links each spec rule to its property. It adds proof that every property started on every instance.
CompareRule Checker or ScoreboardL2 Mid-LevelL3 Senior
You already have a scoreboard comparing what went in with what came out. Why do you also need wire-level rules?

Reveal the Model Answer

They answer different questions. The scoreboard catches beats lost, duplicated or corrupted inside the block, which no rule on the wires can see. The rule checker catches illegal timing at the exact edge, even when the data ends up right. For example, a beat withdrawn and offered again later still matches the scoreboard. But it breaks the hold rule.

Self-Check
Tick each key point you covered in your answer.
Key point 1 They answer different questions. Key point 2 The scoreboard catches beats lost, duplicated or corrupted inside the block, which no rule on the wires can see. Key point 3 The rule checker catches illegal timing at the exact edge, even when the data ends up right. Key point 4 For example, a beat withdrawn and offered again later still matches the scoreboard. Key point 5 But it breaks the hold rule.

What Interviewers Listen For (Mid-Level)
A good mid-level answer gives one bug that only the scoreboard catches and one that only the rule checker catches.
- Lesson P1.11Capstone: The Generic Link Bug Hunt
- Problem P1.11.3The Beat That Arrived Late
Prove ItSolve P1.10.1: Properties for the LinkSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem P1.10.1

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"If valid is held, the beat is held."

The twin keeps valid high and swaps the data during the stall. The hold rule reports 0 failures, and the stable rule reports 1. The sink takes the wrong byte.

Run It

RUNVerilator · simulator service

Edit the code, then run it

Expected: edge 4: sink took b2 hold rule failures: 0 stable rule failures: 1 FAIL: the hold-only checker passed a beat whose data changed during the stall

// The checker has only the hold rule. The source keeps valid high through a stall
// but swaps the data at edge 4 (the beat 'a1' becomes 'b2' before the sink takes it).
module tb;
  logic clk = 0, valid = 0, ready = 0;
  logic [7:0] data = 0;
  int cyc = 0, hold_fail = 0, stable_fail = 0, taken = 0;
  always #5 clk = ~clk;
  always @(posedge clk) cyc <= cyc + 1;
  // the only rule in the checker under review
  hold_rule:   assert property (@(posedge clk) valid && !ready |=> valid)
                 else hold_fail++;
  // the rule it is missing
  stable_rule: assert property (@(posedge clk) valid && !ready |=> $stable(data))
                 else stable_fail++;
  always @(posedge clk) if (valid && ready) begin taken++; $display("edge %0d: sink took %h", cyc, data); end
  initial begin
    @(posedge clk); #1 valid = 1; data = 8'ha1;   // offered, sink stalls
    @(posedge clk); @(posedge clk); #1 data = 8'hb2; // still valid, data swapped mid-stall
    @(posedge clk); #1 ready = 1;
    @(posedge clk); #1 valid = 0; ready = 0;
    repeat (2) @(posedge clk);
    $display("hold rule failures:   %0d", hold_fail);
    $display("stable rule failures: %0d", stable_fail);
    if (hold_fail == 0 && stable_fail > 0)
      $display("FAIL: the hold-only checker passed a beat whose data changed during the stall");
    $finish;
  end
endmodule

Tool as Truth

"It never fired across the regression, so the sources are fine."

In the twin, a source withdraws every stalled offer. With ready always 1, it shows 0 failures, because no attempt ever starts. One test with a toggling ready gives 5 failures.

Run It

RUNVerilator · simulator service

Edit the code, then run it

Expected: ready always 1: beats=9 attempts=0 hold failures=0 ready toggling: beats=1 attempts=5 hold failures=5 FAIL: the source that passed with ready always 1 breaks the hold rule 5 times

// A buggy source: if its beat is not taken in the first cycle, it withdraws valid.
// Run 1 keeps ready high (as every test in the regression did); run 2 adds one stall.
module tb;
  logic clk = 0, valid = 0, ready = 1, stall_test = 0, rst = 0;
  int attempts = 0, fails = 0, beats = 0;
  always #5 clk = ~clk;
  hold_rule: assert property (@(posedge clk) disable iff (rst) valid && !ready |=> valid) else fails++;
  always @(posedge clk) begin
    if (valid && !ready) attempts++;
    if (valid && ready) beats++;
    // the bug: an offer lives for at most one stalled edge
    valid <= (valid && !ready) ? 1'b0 : 1'b1;
    ready <= stall_test ? !ready : 1'b1;          // run 2: ready toggles
  end
  int seen = 0;
  task report(string name);
    $display("%s beats=%0d attempts=%0d hold failures=%0d", name, beats, attempts, fails);
    seen = fails; beats = 0; attempts = 0; fails = 0;
  endtask
  initial begin
    repeat (10) @(posedge clk);
    #1 report("ready always 1:");
    rst = 1; stall_test = 1; @(posedge clk); #1 rst = 0;
    repeat (10) @(posedge clk);
    #1 report("ready toggling:");
    if (seen > 0) $display("FAIL: the source that passed with ready always 1 breaks the hold rule %0d times", seen);
    $finish;
  end
endmodule

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Is the Hold Rule Enough?

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