← Protocols Interviews

Interview Question · Code Reading

The Monitor That Saw Too Many Beats

L0 FresherL1 Juniorhandshakemonitor

The Question

The interviewer asks

A monitor does if (valid) beats++; on every rising edge. The scoreboard says the DUT sent extra data. Who is wrong?

systemverilog
always @(posedge clk) begin
  if (valid) beats++;
end
Reveal the Model Answer

The monitor is wrong. A held offer keeps valid high on every stalled cycle, so counting valid adds one phantom beat per stall. A beat is an edge where valid and ready are both high. In the twin, the link carries three beats with three stalled cycles. Counting valid gives 6, counting rising edges of valid gives 2, and counting handshakes gives 3.

Three Beats, Two StallsWatch the pill: it moves only in a cycle where valid and ready are both 1.
validdatareadySourceoffers beatsSinktakes beats

A lit wire carries a 1. A pill is a transfer in that cycle; slots are the entries held.

01234567clkvalidreadydataxa1xb2c3
  1. Cycle 1

    The source raises valid with a1. ready is 0, so the offer waits.

  2. Cycle 2

    Still waiting. valid and a1 are unchanged: an offer, once made, is held.

  3. Cycle 3

    ready is 1 at this edge. The beat moves, exactly once.

  4. Cycle 4

    ready stays 1 but valid is 0. Nothing moves: ready alone is permission, never a transfer.

  5. Cycle 5

    Both are 1 in the first cycle of the offer, so b2 moves with no stall at all.

  6. Cycle 6

    c3 is offered while the sink is busy again.

  7. Cycle 7

    Taken. Three beats, three cycles where both wires were 1.

Cycles with valid high: 6. Rising edges of valid: 2. Edges where both are 1: 3, the true beat count.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Fresher)

A good fresher answer changes the counting condition to valid && ready, so only real handshakes count.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

What IfProve ItCompareScale It

  1. The Monitor That Saw Too Many Beats
  2. What IfFrom Beats to TransactionsL0 FresherL1 Junior

    The link carries bursts of 1 to 16 beats. How does the monitor know where one transaction ends?

    Reveal the Model Answer

    With a last flag on the final beat, or by counting against a length sent with the request. last lets the receiver and the monitor find where transactions end without knowing the length. A checker spots a short or long burst by comparing the count at last with the requested length. AXI does both: AxLEN in the request, and WLAST or RLAST on the data.

    Four Handshakes, One TransactionA burst of four beats on the link. last marks the final beat, so the sink knows where the transaction ends.
    validdatalastreadySourceone request, four beatsSinkcollects the burst

    Each pill is one beat. The slots collect the burst; last lights on the fourth beat.

    012345clkvalidreadydataxa0a1a2a3xlast
    1. Cycle 1

      Beat 1 of 4: one handshake, one beat. A monitor that reports per handshake sends its first item now.

    2. Cycle 3

      Beat 3. The sink has three of the four beats and no idea yet that a fourth is coming.

    3. Cycle 4

      Beat 4 carries last. The sink knows the burst ended, and a transaction-level monitor reports once, with all four beats.

    last marks the fourth beat, so the sink and the monitor know where the transaction ends.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Fresher)

    A good fresher answer names the last flag that marks the final beat of a transaction.

  3. What IfA Burst Without Its Last FlagL1 Junior

    What if the sender forgets to raise last on the final beat?

    Reveal the Model Answer

    The receiver and the monitor see one long transaction, and the next burst's beats join it. A checker that compares the beat count with the requested length catches it once the count passes the length. Without that check, the fault shows up later as a corrupted packet.

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "The receiver counts beats, so last is only a hint."

    Many receivers end a transaction on last alone. A missing last merges two transactions into one.

    Source Lesson P1.4 key points

  4. CompareWhy the Monitor Ignores the DriverL1 JuniorL2 Mid-Level

    Why not let the driver tell the scoreboard what it sent, instead of building a separate monitor?

    Reveal the Model Answer

    Because the driver reports what it meant to send, not what the wires carried. A driver bug, such as dropping valid during a stall, would be invisible. A passive monitor rebuilds transactions from the wires alone. So the same monitor also works at subsystem level, where the agent is passive and another block drives the link.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer says a bug inside the driver would stay hidden if the driver reported its own work.

  5. Scale ItMeasuring Throughput from the MonitorL2 Mid-LevelL3 Senior

    The architects want proof that the link sustains 90% throughput under realistic backpressure. How do you get it from your bench?

    Reveal the Model Answer

    Have the monitor count handshakes, stalled cycles (valid && !ready) and idle cycles (!valid) over a window. Report beats per cycle for each link. Separate idles caused by the source from stalls caused by the sink, because they have different owners. Run it with the traffic profile the architects specify. Track it as a regression metric with a threshold.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer has the monitor count three kinds of cycle: handshake cycles, stalled cycles and idle cycles.

  6. Prove ItSolve P1.11.5: A Monitor for the LinkSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P1.11.5

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"valid is high once per beat, so counting it is fine."

Only when the sink is always ready. The twin counts 6 for 3 beats once the sink stalls.

Run It
RUNIcarus Verilog · in your browser
Edit the code, then run it
Expected: monitor A (valid high): 6 beats monitor B (valid rises): 2 beats monitor C (valid && ready): 3 beats FAIL: counting valid high reports 6 beats for 3 transfers FAIL: counting valid rising edges reports 2 beats for 3 transfers

Missed Corner

"Count on the rising edge of valid instead."

Back-to-back beats keep valid high across several transfers. So an edge detector undercounts: 2 for 3 beats in the twin.

Run It
RUNIcarus Verilog · in your browser
Edit the code, then run it
Expected: monitor A (valid high): 6 beats monitor B (valid rises): 2 beats monitor C (valid && ready): 3 beats FAIL: counting valid high reports 6 beats for 3 transfers FAIL: counting valid rising edges reports 2 beats for 3 transfers

Learn It, Then Prove It