Interview Question · Concept
I2C Multi-Controller Arbitration
The Question
The interviewer asks
Two controllers start a transfer at the same moment, one to 0x50 and one to 0x58. How does I2C decide who wins, and what happens to the loser's message?
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Reveal the Model Answer
Both drive SDA bit by bit, and compare the wired-AND line with what they sent while SCL is high. The first controller to send a 1 and read a 0 has lost, and it releases SDA at once. Until then both sent identical bits, so nothing is lost and the winner's message is intact. Address 0x58 loses on the fourth address bit. The loser may clock to the end of that byte, and retries when the bus is free.
A low lane of 1 pulls the net down. The pull-up raises it only when every device releases.
Read phases and sample points (quarter bit)
- bit 0: columns 1 through 4.
- bit 1: columns 5 through 8.
- bit 2: columns 9 through 12.
- bit 3: columns 13 through 16.
- bit 4: columns 17 through 20.
- bit 5: columns 21 through 24.
- bit 6: columns 25 through 28.
- bit 7: columns 29 through 32.
- SDA sampled at 3, 7, 11, 15, 19, 23, 27, 31.
- Cycle 3
The first bit sent (band
bit 0): both send 1. Nobody pulls, the line reads 1, and both stay in. - Cycle 15
The 4th bit sent (band
bit 3): controller 1 sends 0 and pulls the line low; controller 2 sent 1 and reads 0. It drops out here. - Cycle 31
Controller 1 finishes its byte alone. Its address went out unharmed, so the target it wanted answers.
Generated and decoded back: the decoder finds the drop on the 4th bit sent. The bench measured the same SCL pulse: other drops out at SCL pulse 4.
A sends 50 W 3c, B sends 58 W c3 B lost at SCL pulse 4 bus: S 50 W A 3c A PSelf-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer explains the bit-by-bit compare on SDA. A 0 beats a 1, so the lower value wins that bit.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains why no data is lost, and that arbitration continues into the data if the addresses match. It knows a loser that is also a target must switch to target mode at once.
What Interviewers Listen For (Senior)
A good senior answer knows the collisions UM10204 leaves undefined, such as a repeated START or STOP against a data bit. It knows there is no priority except the bits themselves.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItScale It
- I2C Multi-Controller Arbitration
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WhyThe Loser May Be the TargetL2 Mid-Level
Your controller also has a target address. It loses arbitration during the address byte. What must it do next, and why?
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Reveal the Model Answer
It must switch to target mode at once and keep decoding the address. The winner may be addressing this very device. If it waits as an idle controller until the bus is free, it misses its own address. The winner then sees a NACK. Separately, it must not drive any more bits of its own message.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer gives the reason: the winner may be addressing this device. It switches to target mode at once, in the same byte.
What Interviewers Listen For (Senior)
A good senior answer turns it into a test. One controller's target address equals the other controller's destination, and the test checks that the loser sends the ACK.
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What IfWhen the Losing Controller May RetryL2 Mid-Level
What if the losing controller starts its own transfer again right after it loses?
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Reveal the Model Answer
It must wait until the bus is free. The bus counts as busy from the START until a set time after the STOP, and a repeated START keeps it busy. So the loser waits for the winner's STOP and the bus-free time. A START any earlier breaks the winner's message.
Self-Check
Tick each key point you covered in your answer.
Misconception
"The loser can start again as soon as it has lost."
The winner's message is still on the bus. A new START in the middle of it corrupts that message.
Source NXP UM10204 rev. 7 §3.1.8 Arbitration
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Break ItWhere Arbitration Is UndefinedL2 Mid-LevelL3 Senior
Is there any collision I2C arbitration cannot resolve?
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Reveal the Model Answer
Yes. UM10204 leaves three collisions undefined while arbitration is still running. In two of them, one controller sends a repeated START or a STOP while the other sends a data bit. In the third, one sends a repeated START against a STOP. Arbitration works only when both still send bits in the same position of the same format.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names the three collisions where arbitration is undefined.
What Interviewers Listen For (Senior)
A good senior answer draws the design rule: transfers of different formats must not collide unnoticed. A bench marks these cases out of scope instead of accepting any result as a pass.
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Scale ItVerifying a Multi-Controller I2C IPL3 SeniorL4 Staff
You own a multi-controller I2C controller IP. How do you verify arbitration and clock synchronisation to sign-off?
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Reveal the Model Answer
Build a two-controller bench with a reference controller and the DUT on wired-AND lines. Cover a loss at every address and data bit position and identical messages that complete together. Add a loss while addressed as a target, the clock-to-end-of-byte rule, and unequal LOW/HIGH periods for synchronisation. Check from the driver view that the loser never drives after losing. Back it with a formal proof on an abstraction.
Fault What exposes it Loser keeps driving SDA Driver-view check after the losing bit Loser clocks past the byte Count SCL pulls by the loser after loss No switch to target mode Winner addresses the loser Drops on identical bits Identical messages from both Compares while SCL is low Data that changes during SCL low Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer covers a loss at every bit position, identical messages and the loser-becomes-target case. It checks, from each device's drive enable, that the loser stops driving.
What Interviewers Listen For (Staff)
A good staff answer combines simulation with a formal property that the loser withdraws, and states what the formal model leaves out. Sign-off means both sets of seeded faults are caught and every loss position is covered.
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Prove ItSolve P8.6.3: A Controller That Withdraws on Arbitration LossSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"Arbitration is decided during the address byte."
Only if the addresses differ. Two controllers addressing the same target go on comparing through the data. Here both address 0x50. A loses at pulse 15, inside the data byte, and the bus carries B's 0x3a intact.
Run It
A sends 50 W 3c, B sends 50 W 3a A lost at SCL pulse 15 bus: S 50 W A 3a A P FAIL: arbitration ran past the address byte, decided at SCL pulse 15Misconception
"A bus arbiter or a priority register decides."
There is no central controller and no priority order. The outcome follows only from the address and data bits the controllers send.
Source NXP UM10204 rev. 7 §3.1.8 Arbitration
Spec Misquote
"The loser must stop clocking immediately."
The loser releases SDA at once. But it may keep generating clock pulses until the end of the byte in which it lost. It must not start again until the bus is free.
Source NXP UM10204 rev. 7 §3.1.8 Arbitration