Interview Question · Concept
Clock Stretching
The Question
The interviewer asks
What is clock stretching in I2C, and what must the controller do for it to work?
You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
A target that needs time holds SCL low. SCL is a wired-AND, so the line stays low after the controller lets go. The controller must read SCL back, and start timing its HIGH only once SCL really is high. A controller that times HIGH from its own release samples SDA too early. The target still holds the clock, so the controller reads a wrong byte. Stretching is optional for targets and has no time limit in I2C.
Read phases and sample points (quarter bit)
- START: columns 2 through 3.
- 0xa0 + ACK: columns 4 through 39.
- 0xa5 + ACK: columns 40 through 75.
- stretch (5 quarters): columns 76 through 80.
- START: columns 81 through 84.
- 0xa1 + ACK: columns 85 through 120.
- 0xa5 + NACK: columns 121 through 156.
- STOP: columns 157 through 160.
- SDA sampled at 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 87, 91, 95, 99, 103, 107, 111, 115, 119, 123, 127, 131, 135, 139, 143, 147, 151, 155.
- Cycle 74
The target acknowledges the pointer byte 0xA5.
- Cycle 76
Then it holds SCL low (
tgt_scl_low= 1). The controller has let go, but the wire stays low. - Cycle 83
When the target lets go, SCL rises and the controller carries on with the Sr.
Generated and decoded back. The target holds SCL low after its ACK, and the controller waits until SCL really rises.
A low lane of 1 pulls the net down. The pull-up raises it only when every device releases.
- Cycle 18
The ACK finishes. The target releases SDA and takes SCL, exactly as before.
- Cycle 31
The controller lets go of SCL for 1 ns, samples SDA, and pulls again: a "clock" that never reaches the wire.
- Cycle 58
Two controller bit cycles have passed without a wire clock. The first real SCL rise samples bit 5 of the pointer, so the peers disagree about their byte position.
Measured. This controller times its HIGH from its own release, not from the wire. SCL never rose during the stretch, so the bytes slipped.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says the target holds SCL low and the controller waits. It knows stretching can happen after a byte's ACK or at a single bit.
What Interviewers Listen For (Mid-Level)
A good mid-level answer states the read-back rule exactly. It explains the failure without it: a lost clock pulse and a shifted byte. It knows a stretching target must set up SDA before it lets SCL go.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompare
- Clock Stretching
-
WhyOne Rule, Two FeaturesL2 Mid-Level
The same "read SCL back" rule makes clock synchronisation between two controllers work. Explain how.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
On a wired-AND SCL, every controller starts counting LOW when the line falls. But the line rises only when the last one lets go. Each waits for SCL high before counting HIGH, and the first to finish HIGH pulls it low again. So the bus clock gets the longest LOW and the shortest HIGH of all controllers. A stretching target is just another device with a long LOW.
Two Clocks, One Wire: The Longest LOW, the Shortest HIGH ctrl(TLOW 1300, THIGH 1200) andother(TLOW 2600, THIGH 1500) both drive SCL during the address byte. 100 ns per column.All cyclesA low lane of 1 pulls the net down. The pull-up raises it only when every device releases.
- Cycle 2
SCL falls. Both controllers start counting their own LOW time from this edge and both pull.
- Cycle 15
ctrl's 1300 ns are up and it lets go.otherstill pulls, so SCL stays low andctrlwaits. - Cycle 29
otherlets go too and SCL rises: a LOW of 2601 ns,other's. Both now count HIGH. - Cycle 41
ctrlfinishes its HIGH first and pulls: a HIGH of 1209 ns,ctrl's. That fall restarts both LOW counts.
Measured on the bench:
SCL LOW 2601 ns,SCL HIGH 1209 ns. The extra ns come from the controllers polling SCL every 10 ns.Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains, from the wired-AND, why the bus clock gets the longest LOW and the shortest HIGH. It links this to clock stretching.
What Interviewers Listen For (Senior)
A good senior answer notes what this means for testing. A controller that skips the read-back passes single-controller tests and fails only with a second controller or a stretching target.
- Cycle 2
-
What IfA Target That Never Lets GoL2 Mid-LevelL3 Senior
A target holds SCL low and never releases it. I2C has no time-out. What should your controller do, and how would you verify it?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
I2C sets no limit, so the controller IP should carry its own configurable time-out. It should give up and report, not hang. With SCL stuck low, clocking out is impossible, so UM10204 points to a hardware reset input or a power cycle. To verify, use a target model that never releases. Check that the controller times out, flags the error and leaves SCL released.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer adds a time-out and an error status to the controller. It knows nine clock pulses cannot help when SCL itself is stuck.
What Interviewers Listen For (Senior)
A good senior answer makes the time-out a system decision, such as the SMBus 35 ms if the platform is SMBus. It sends the error to software that can reset the device, and tests the never-release case.
-
Break ItA Clock-Stretch Time-Out That Is Too ShortL2 Mid-Level
Break it: you set the controller's stretch time-out to 1 ms. Which legal target does that break?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Any target whose datasheet allows a longer stretch. I2C sets no limit on stretching, so a 1 ms limit turns legal behaviour into a reported error. Set the limit from the slowest target's datasheet. Use SMBus's 35 ms only when the system really uses SMBus devices.
Self-Check
Tick each key point you covered in your answer.
Spec Misquote
"I2C allows 35 ms of clock stretching."
That is the SMBus time-out. I2C itself sets no limit at all.
Source NXP UM10204 rev. 7 §4.2.2 Time-out feature
-
CompareStretching on I3CL1 JuniorL2 Mid-Level
Can a target stretch the clock on I3C? What replaces it?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
No. In I3C only the controller drives SCL, and legacy I2C targets on an I3C bus may not stretch. The controller may stall instead, holding SCL low in only four places. They are the ACK/NACK slot, a write's parity bit, a read's T-bit and the first bit of an assigned address in DAA. The absolute maximum stall is 15 ms.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says I3C targets cannot stretch the clock, because only the controller drives SCL.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names the places where the I3C controller may stall SCL. It explains why stalls are discouraged: they cut bus capacity and delay in-band interrupts.
-
Prove ItSolve P8.5.1: Wait for the Stretched ClockSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"The controller just drives its clock; stretching is the target's business."
If the controller does not read SCL back, its first HIGH vanishes under the target's stretch. Then it samples SDA early. Here it reads 0x9a instead of 0x35, and SCL rose only 7 times for 8 bits.
Run It
ignores SCL : read 9a, SCL rises 7 FAIL: read 9a, the target sent 35See the Fix
`timescale 1ns/1ns
// Clock stretching on a wired-AND SCL. The target holds SCL low for 3000 ns at the start of a read
// byte while it fetches 0x35, puts bit 7 on SDA 200 ns before letting go, then moves to the next
// bit after every falling SCL edge. The controller reads the byte twice: reading SCL back, and not.
module tb;
logic c_scl_low = 0, t_scl_low = 0, t_sda_low = 0;
wire scl = !(c_scl_low | t_scl_low); // open drain: low if anyone pulls
wire sda = !t_sda_low;
localparam int THALF = 1250; // controller LOW and HIGH, 400 kHz
byte data = 8'h35;
int rises;
event go;
always @(posedge scl) rises++;
initial forever begin
@go;
begin : target
t_scl_low = 1; // stretch from the start of the byte
#2800 t_sda_low = !data[7];
#200 t_scl_low = 0;
for (int i = 6; i >= 0; i--) begin @(negedge scl); #100 t_sda_low = !data[i]; end
@(negedge scl); #100 t_sda_low = 0; // let go of SDA for the controller's ACK
end
end
task automatic ctrl_read(input bit reads_back, output byte v);
for (int b = 7; b >= 0; b--) begin
c_scl_low = 1; #THALF;
c_scl_low = 0; // let go of SCL
if (reads_back) wait (scl === 1'b1); // count tHIGH only once SCL is really high
#(THALF/2) v[b] = sda; // sample in the middle of the HIGH
#(THALF/2);
end
c_scl_low = 1;
endtask
task automatic one(input bit reads_back);
byte v;
rises = 0;
-> go; #0;
ctrl_read(reads_back, v);
#2000 disable target; // a target still waiting for an edge is abandoned
$display("%s: read %h, SCL rises %0d", reads_back ? "reads SCL back" : "ignores SCL ", v, rises);
if (v === data) $display("PASS: read %h as sent", v);
else $display("FAIL: read %h, the target sent %h", v, data);
c_scl_low = 0; t_scl_low = 0; t_sda_low = 0; #5000;
endtask
initial begin
#10;
one(1);
$finish;
end
endmodule
Prints: reads SCL back: read 35, SCL rises 8 PASS: read 35 as sent
Spec Misquote
"Every I2C target stretches the clock."
Stretching is optional, and UM10204 notes most targets have no SCL driver at all. A controller still has to handle it, unless it knows no device on its bus stretches.
Source NXP UM10204 rev. 7 §3.1.9; Table 3 note 2
Spec Misquote
"There is a 35 ms stretch limit in I2C."
That is SMBus. I2C sets no limit on how long a target may hold SCL. SMBus caps it at 35 ms and resets devices on time-out.
Source NXP UM10204 rev. 7 §4.2.2 Time-out feature