Interview Question · Concept
I3C In-Band Interrupts
The Question
The interviewer asks
How does an I3C target raise an interrupt without an interrupt pin? Walk me through the request and the controller's choices.
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Reveal the Model Answer
The target puts its own address with R into the arbitrable header after a START. If the bus stays free for the Bus Available time, the target pulls SDA low itself. The controller then completes the START and drives the clock. The controller has three answers. It can ACK and read the mandatory byte, if BCR bit 2 promises one. Or it can NACK so the target retries later, or NACK and disable its events with DISEC.
- Cycle 5
The bus has been free for longer than tAVAL (1 µs, Table 58). Target1 pulls SDA low: a START request.
- Cycle 7
The controller pulls SDA too and then SCL, which completes the START (MIPI §5.1.2.2).
- Cycle 17
Header 08/R in open drain. The controller sends 7E and lets go on its first bit; target1's 0 wins.
- Cycle 59
The controller ACKs: an accepted IBI. After the SCL rise the target takes SDA over (§5.1.2.3.2).
- Cycle 67
The mandatory byte 0xA5 in push-pull, then T = 0 and STOP. BCR bit 2 promised this byte (Table 6).
Measured: CTRL START request from a target at 47316, CTRL IBI from 08 accepted, MDB a5 T0, I3C S 08 R A a5 T0 P.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer describes the header arbitration and the START the target makes itself. It gives the controller's three answers, including reading the mandatory byte.
What Interviewers Listen For (Senior)
A good senior answer discusses latency from bus traffic and controller stalls, and priority by address. It says what the controller does when it needs the bus for something more urgent.
What Interviewers Listen For (Staff)
A good staff answer weighs in-band interrupts against separate interrupt wires for the whole system. It trades saved pins and board layers against a firm latency limit for safety-critical events.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
What IfProve ItBreak ItCompareScale It
- I3C In-Band Interrupts
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CompareIBI Versus an Interrupt PinL2 Mid-LevelL3 Senior
Why would an architect choose in-band interrupts over one interrupt line per sensor? When would you keep the pin?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
IBI saves a host pin and a board trace per device. The interrupt carries the source's address and often a data byte, so the host need not poll to find who asked. The price is latency that depends on the bus. A request waits for a START or the Bus Available time, controller stalls add delay, and a lower-address target wins collisions. Keep a pin where worst-case latency must stay tightly bounded.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer gives the benefits, fewer pins and the source named in the interrupt, and the cost, latency.
What Interviewers Listen For (Senior)
A good senior answer puts numbers on the waits: Bus Available time, stalls up to the spec limits and higher-priority traffic. It ties the choice to the system's latency budget.
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What IfTwo Interrupts at OnceL2 Mid-Level
Two targets raise an IBI after the same START while the controller wanted to address 7E. Who wins, and what do the others do?
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Reveal the Model Answer
The header is open drain, so the lowest address on the wire wins. Any assigned dynamic address (0x03 to 0x7B) is lower than 7E. So an interrupting target always beats the controller's broadcast header. Between targets, the lower address wins. The losers may try again, but only after the next Bus Available condition, not on a repeated START.
The Controller's Header Loses to an IBIMeasured, 40 ns per column. Target2 (0x09) raised its request while the bus was busy; the controller starts its next frame 40 ns after STOP (a pure bus: bus free is tCAS) and sends 7E. All cycles- Cycle 8
Bit A6: the controller sends 1 (lets go); target2 sends 0 (pulls). SDA is 0: the controller has lost (MIPI §5.1.2.2.1).
- Cycle 26
The controller stays silent for the rest of the header, but keeps clocking: only it drives SCL.
- Cycle 50
RnW = 1: an interrupt request from 0x09, not a controller-role request.
- Cycle 56
The controller ACKs and will read the mandatory byte before it goes back to its own write.
Measured:
I3C S 09 R A a5 T0 Sr 7e W A Sr 09 W A 10 T0 Sr 09 R A 5a T0 P. The broadcast address 7E has lower priority than any interrupt (§5.1.6.4).Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer applies the lowest-address-wins rule and the rule for when a loser may retry.
What Interviewers Listen For (Senior)
A good senior answer turns it into coverage. It covers target against target, target against 7E, and a loser that retries too early. Each case gets a check on who drives the line.
- Cycle 8
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What IfWhen the Controller Refuses an IBIL2 Mid-Level
What if the controller NACKs the winning IBI? What does the target do next?
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Reveal the Model Answer
A plain NACK refuses only this request, and the target tries again after the Bus Available condition. To stop the requests, the controller NACKs, sends a repeated START and then DISEC with DISINT set. A controller that NACKs forever without DISEC wastes the bus on retries.
Self-Check
Tick each key point you covered in your answer.
Spec Misquote
"A NACKed target drops the interrupt for good."
A plain NACK only denies this attempt. The target retries after Bus Available unless DISEC disables its interrupts.
Source MIPI I3C Basic v1.0 §5.1.6.2
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Break ItThe Missing Mandatory ByteL2 Mid-LevelL3 Senior
A target's BCR says a mandatory byte follows each IBI, but the target sends none. What does the bus show?
log Illustrative IBI observation Discovered BCR: mandatory data byte required Target requests IBI; controller accepts Target supplies no mandatory data byte2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
After its ACK, the controller releases SDA and expects the target to drive the byte. Nobody drives, so the keeper or pull-up lets SDA rise while SCL is high. That is a STOP on the wire. A decoder closes the frame early, and a controller that carries on reads 0xFF. The fix is in the target, but only a checker that knows BCR[2] can flag it directly.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains that the released SDA rising while SCL is high forms an accidental STOP.
What Interviewers Listen For (Senior)
A good senior answer writes the check from BCR. After an accepted interrupt from a target with BCR[2] set, a byte must follow. It covers both BCR settings.
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Scale ItVerifying an I3C TargetL3 SeniorL4 Staff
What must an I3C target verification environment contain beyond private reads and writes?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
It needs several devices, because most I3C faults involve more than one device. Use two targets with near-identical IDs for DAA ties, and two simultaneous IBIs for header contention. Add a legacy I2C neighbour for the coexistence and no-stretch rules, and HDR enter and exit followed by an SDR read. Check with a wire checker and a driver view that shows who drives a 1, for push-pull faults. Also self-check effects such as addresses assigned and bytes read.
Stimulus Faults it misses Private write and read only DAA ties, parity, missing IBI byte, missed HDR exit, early push-pull, legacy stretching Everything except interrupts Missing IBI byte, early push-pull in the header Everything except the legacy target Legacy stretching Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer lists the multi-device test programs. It uses both a wire checker and a view of who drives each line.
What Interviewers Listen For (Staff)
A good staff answer argues sign-off from a bank of seeded faults that the full program set catches. It says what each smaller set of programs would miss.
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Prove ItSolve P9.6.1: Send the Mandatory IBI ByteSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"The target drives SCL to send its interrupt."
Only the controller drives SCL in I3C. The target can only pull SDA to request a START. It then shifts its address out on the controller's clock.
Source MIPI I3C Basic v1.0 §5.1.2, §5.1.6.2
Spec Misquote
"A target can raise an IBI after a repeated START."
Only the header after a START is arbitrable. After a repeated START, the header is push-pull, and targets must not drive their address into it.
Source MIPI I3C Basic v1.0 §5.1.6.2; §5.1.2.2.4
Half-Truth
"If the controller ACKs, it can skip the mandatory byte."
When BCR[2] is 1, the byte follows the ACK in push-pull. The controller cannot avoid receiving it.