I3C Versus I2C

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

1. I3C Versus I2C
2. WhyWhere I3C Keeps Open DrainL1 JuniorL2 Mid-Level

   Why does I3C go push-pull for data, and why not everywhere?

   Reveal the Model Answer

   A push-pull 1 does not wait for a pull-up resistor to charge the bus. So bits get much shorter: 80 ns push-pull against 240 ns open drain on the lesson bench. Where several devices may drive at once, a 0 must win and a 1 must lose quietly, as in a wired-AND. So these stay open drain: the header after START, where targets may raise interrupts, plus ACK slots and address assignment. The header after a repeated START, and data, are push-pull.

   1. Open drain

      The arbitrable header, every ACK slot and DAA: places where two devices may drive at once (MIPI §5.1.2.2.1, §5.1.4.2).

   2. Push-pull

      The header after Sr and all SDR data: one transmitter, so it drives both levels (§5.1.2, §5.1.2.2.4).

   Read the diagram as text

   • S + header: open drain: a target may win
   • ACK slots: open drain: any target may answer
   • Sr + header: push-pull: nobody else may speak
   • Write data + T: push-pull: the controller
   • Read data + T: push-pull: the target
   • DAA: open drain: IDs arbitrate

   • S + header → ACK slots
   • Sr + header → Write data + T
   • Write data + T → Read data + T
   • ACK slots → DAA

   Open drain wherever two devices may drive SDA at once. Push-pull wherever exactly one device drives.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A push-pull 1 does not wait for a pull-up resistor to charge the bus. Key point 2 So bits get much shorter: 80 ns push-pull against 240 ns open drain on the lesson bench. Key point 3 Where several devices may drive at once, a 0 must win and a 1 must lose quietly, as in a wired-AND. Key point 4 So these stay open drain: the header after START, where targets may raise interrupts, plus ACK slots and address assignment. Key point 5 The header after a repeated START, and data, are push-pull.

   What Interviewers Listen For (Junior)

   A good junior answer links push-pull to speed and open drain to arbitration.

   Half-Truth

   "Open drain in the header is only for I2C compatibility."

   The header after START is arbitrable in I3C itself. Targets may drive their own address into it to request an interrupt or mastership. So it needs a wired-AND.

   • Lesson P9.3Open-Drain and Push-Pull Phases
   • Problem P9.3.1Release SDA for the Header ACK
3. What IfA Legacy I2C Target on an I3C BusL1 JuniorL2 Mid-Level

   You must keep an old I2C sensor on the new I3C bus. What conditions does it have to meet, and what happens if it lacks a spike filter?

   Reveal the Model Answer

   It must be a target only, with a static address, Fast-mode support and no clock stretching. A true 50 ns spike filter on SCL hides the short I3C clock highs from it. Then the bus can run I3C at full speed, which is called a mixed fast bus. Without the filter, the device sees I3C traffic as clocks. The bus speed then drops to what the slowest unfiltered legacy device tolerates.

   1. Fm passes

      An I2C clock high lasts far longer than 50 ns, so the legacy target sees every bit (MIPI Table 57).

   2. SDR does not

      On a mixed fast bus the I3C SCL high stays under tDIG_H_MIXED, 45 ns at most (Table 59), and never gets through.

   Read the diagram as text

   • I2C message: SCL high 1200 ns (Fm)
   • I3C message: SCL high 40 ns (SDR)
   • 50 ns filter: drops shorter pulses
   • 50 ns filter: drops shorter pulses
   • Clocks: the target decodes the byte
   • SCL looks low: no bits, nothing to answer

   • I2C message → 50 ns filter
   • 50 ns filter → Clocks
   • I3C message → 50 ns filter
   • 50 ns filter → SCL looks low

   MIPI I3C Basic v1.0 §5.1.2.4 and Figure 45. The bench models the filter as a 50 ns inertial delay on SCL and SDA.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 It must be a target only, with a static address, Fast-mode support and no clock stretching. Key point 2 A true 50 ns spike filter on SCL hides the short I3C clock highs from it. Key point 3 Then the bus can run I3C at full speed, which is called a mixed fast bus. Key point 4 Without the filter, the device sees I3C traffic as clocks. Key point 5 The bus speed then drops to what the slowest unfiltered legacy device tolerates.

   What Interviewers Listen For (Junior)

   A good junior answer names the two rules: the legacy target must not stretch the clock, and it needs a spike filter.

   • Lesson P9.2SDR Frames and Legacy I2C Coexistence
   • Lesson P9.1I3C in One Picture
   • Problem P9.1.1Keep Legacy and SDR Reads Distinct
   • Problem P9.8.1Catch Contention and Legacy Stretching
4. CompareThe I3C T-Bit Versus the I2C ACKL1 JuniorL2 Mid-Level

   In I2C the ninth bit of a data byte is the receiver's ACK. What is it in I3C SDR?

   Reveal the Model Answer

   The transmitter drives it. On a write, it is odd parity from the controller: the XOR of the eight data bits with 1. Parity lets the target detect a corrupted byte. On a read, it is end-of-data from the target: 0 ends the message, and 1 offers more. So the target decides how much it returns, though the controller may abort after a 1 with a repeated START.

   Read phases and sample points (quarter bit)

   • START: columns 2 through 3.
   • 7e/W (open drain) + ACK: columns 4 through 39.
   • Sr: columns 40 through 43.
   • 08/W (push-pull) + ACK: columns 44 through 79.
   • 10 + T0: columns 80 through 115.
   • 3c + T1: columns 116 through 151.
   • 01 + T0: columns 152 through 187.
   • STOP: columns 188 through 191.
   • SDA sampled at 6, 10, 14, 18, 22, 26, 30, 34, 38, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126, 130, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174, 178, 182, 186.

   1. Cycle 78

      Header ACK: the target pulls SDA in open drain, exactly as in I2C.

   2. Cycle 79

      Handoff: the controller pulls SDA low just after the SCL rise, while the target lets go. Both low for a moment is safe (MIPI §5.1.2.3.1).

   3. Cycle 114

      Ninth bit of 0x10: the controller drives the parity, XOR(data, 1) = 0. The target drives nothing.

   4. Cycle 150

      Ninth bit of 0x3c: four 1s, so parity 1. Still the controller, still push-pull.

   Generated and decoded back. 0x10 and 0x01 each have one 1 bit, so their T-bit is 0. 0x3c has four 1 bits, so its T-bit is 1.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The transmitter drives it. Key point 2 On a write, it is odd parity from the controller: the XOR of the eight data bits with 1. Key point 3 Parity lets the target detect a corrupted byte. Key point 4 On a read, it is end-of-data from the target: 0 ends the message, and 1 offers more. Key point 5 So the target decides how much it returns, though the controller may abort after a 1 with a repeated START.

   What Interviewers Listen For (Junior)

   A good junior answer says the transmitter drives the T-bit: parity on writes, end-of-data on reads.

   Misconception

   "I3C targets ACK every data byte like I2C."

   Only the address header has an ACK. A target that pulls SDA in the ninth bit of a written byte collides with the controller's push-pull parity bit.

   Source MIPI I3C Basic v1.0 §5.1.2.3.3

   • Lesson P9.2SDR Frames and Legacy I2C Coexistence
   • Lesson P8.3Bytes, ACK and NACK
   • Problem P9.2.1Write the SDR Odd-Parity T-Bit
5. What IfA Parity Error on a Written ByteL2 Mid-Level

   What if the target sees a parity error on a byte the controller wrote? What does it do, and how does the controller find out?

   Reveal the Model Answer

   It cannot NACK the byte, because the ninth bit belongs to the controller. Error type S2 says the target ignores the rest and waits for a STOP or a repeated START. The controller sees nothing on the wire. It learns of the error later, from the Protocol Error bit that GETSTATUS returns.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 It cannot NACK the byte, because the ninth bit belongs to the controller. Key point 2 Error type S2 says the target ignores the rest and waits for a STOP or a repeated START. Key point 3 The controller sees nothing on the wire. Key point 4 It learns of the error later, from the Protocol Error bit that GETSTATUS returns.

   Misconception

   "The target NACKs a bad byte, as in I2C."

   In I3C SDR the controller drives the ninth bit of a write as parity. The target has no slot to answer in.

   Source MIPI I3C Basic v1.0 §5.1.2.3.3

   • Lesson P9.2SDR Frames and Legacy I2C Coexistence
   • Problem P9.2.1Write the SDR Odd-Parity T-Bit
6. Break ItHDR Tolerance in I3C BasicL2 Mid-LevelL3 Senior

   Your I3C Basic target supports no HDR mode. Can it ignore HDR entirely?

   Reveal the Model Answer

   No. I3C Basic v1.0 leaves out the HDR (high data rate) modes themselves. But a full I3C controller may still put the bus into HDR for other devices. Every target must detect the HDR entry command and the HDR Exit Pattern, even one with no HDR support. A target that misses the exit treats HDR traffic as SDR and misreads what follows. Feature lists differ between I3C editions, so name the edition you quote.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No. Key point 2 I3C Basic v1.0 leaves out the HDR (high data rate) modes themselves. Key point 3 But a full I3C controller may still put the bus into HDR for other devices. Key point 4 Every target must detect the HDR entry command and the HDR Exit Pattern, even one with no HDR support. Key point 5 A target that misses the exit treats HDR traffic as SDR and misreads what follows. Key point 6 Feature lists differ between I3C editions, so name the edition you quote.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer separates supporting an HDR mode from tolerating one. It says every target must detect the HDR Exit Pattern.

   • Lesson P9.7HDR Patterns and Error Recovery
   • Lesson P9.8Capstone: The I3C Target Bug Hunt
   • Problem P9.7.1Distinguish HDR Restart from Exit
   • Problem P9.8.1Catch Contention and Legacy Stretching
7. Prove ItSolve P9.1.1: Keep Legacy and SDR Reads DistinctSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P9.1.1