Interview Question · Debug
The 300-Byte Page Program
The Question
The interviewer asks
Firmware programs a 300-byte buffer into a W25Q128JV starting at a page boundary. Readback shows the first 44 bytes wrong and the next page still erased. Explain.
Illustrative W25Q128JV readback
Page Program request: 300 bytes from a page boundary
Readback bytes 0-43: differ from expected
Readback bytes 44-255: match
Next page: still erasedYou have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Page Program writes within one 256-byte page. The low address byte wraps inside the page, so bytes 256 to 299 overwrite bytes 0 to 43. The next page is never touched. The driver must split writes at page boundaries. It must send Write Enable (06h) before every program, because WEL clears when a program finishes. It must also raise CS only after a whole byte, and poll BUSY before the next command.
- First pass
Bytes 0 to 255 fill the page from offset 00.
- The wrap
Byte 256 goes back to offset 00. The 44 tail bytes replace the 44 header bytes; the next page never sees them.
Read the diagram as text
- Bytes 0 to 43: the header
- Bytes 44 to 255: the body
- Bytes 256 to 299: the tail
- Offsets 00 to 2B: end up holding the tail
- Offsets 2C to FF: hold the body
- Next page: untouched: FFh
- Bytes 0 to 43 → Offsets 00 to 2B: first
- Bytes 44 to 255 → Offsets 2C to FF
- Bytes 256 to 299 → Offsets 00 to 2B: wraps, overwrites
Arrows are where the payload bytes land. Measured on the bench: offset 00 reads 50h, the first tail byte.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer states that the address wraps inside the page, so the driver must split writes. It names Write Enable before every program and BUSY polling.
What Interviewers Listen For (Senior)
A good senior answer explains why the bug escaped: a lenient flash model agreed with the driver. It demands a strict model and covers offsets and lengths around the page boundary.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItScale It
- The 300-Byte Page Program
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WhyWEL and BUSYL1 JuniorL2 Mid-Level
Why does every program or erase need its own Write Enable, and how does firmware know the operation has finished?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Write Enable (06h) sets WEL, a guard against stray writes. The flash clears it after every program, erase or status write, so each one needs a fresh 06h. After CS rises, the operation runs on its own for milliseconds. Firmware polls status register 1 with 05h until BUSY, bit 0, reads 0. While BUSY, the flash ignores everything except status reads and suspend.
One Program, Frame by FrameOne column pair per CS frame: the frame, then the gap after it. WEL and BUSY are the flash's latches after each frame. All cycles- Cycle 0
06h, Write Enable: WEL goes to 1.
- Cycle 2
02h with the address and one byte. When CS rises the internal program starts: BUSY goes to 1.
- Cycle 4
The controller polls 05h. While BUSY is 1 the flash ignores everything but the status reads.
- Cycle 26
The program is over: BUSY and WEL are both 0. The next write needs a new 06h.
- Cycle 28
Now the flash accepts a read.
Measured: one Page Program of 5Ah, then a read that returns 5Ah. Status reads find BUSY set until the program is over.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says 06h sets WEL and every program or erase clears it. It says firmware polls BUSY.
What Interviewers Listen For (Mid-Level)
A good mid-level answer knows the flash ignores commands while BUSY. So a driver that skips polling loses them without any error.
- Cycle 0
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Prove ItSolve P7.8.1: WEL and BUSY at a Flash Command BoundarySimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Break ItHow the Page Bug EscapedL2 Mid-LevelL3 Senior
Walk me through how the page-wrap bug escaped your flash-model tests and what you would change.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The model shared the driver's wrong belief, a linear address. So the two agreed, and the test checked nothing the datasheet says. Fix the model first: feed it stimulus the datasheet forbids or defines unusually, and expect the datasheet's result. Examples are a program past a page, a program without 06h and a quad read with QE clear. Then cover page offset × length, including lengths that cross the boundary.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer sees that the model and the design shared the same wrong assumption.
What Interviewers Listen For (Senior)
A good senior answer checks the model against the datasheet with forbidden stimulus. It makes boundary coverage an exit criterion.
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Prove ItSolve P7.10.2: Choose Flash Programs That Expose Hidden FaultsSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
What IfProgramming over Old DataL1 JuniorL2 Mid-Level
What if firmware programs a location that already holds data, without erasing first?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The datasheet defines Page Program only on erased locations, which read FFh. So the result is not something to rely on. In practice, programming can only clear bits, never set them. To get 1s back you must erase, and the smallest erase on this flash is a 4 KB sector. So updating one byte means a read, a sector erase and a reprogram.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says the location must be erased before it is programmed.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says only erased locations are specified. It plans a read, a 4 KB sector erase and a rewrite.
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Scale ItVerifying an SPI Flash ControllerL2 Mid-LevelL3 Senior
You verify a QSPI flash controller that does reads, page programs and erases. What is in your bench, and which bugs would still escape?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Use a wire monitor for every supported mode and lane width. Add wire checks that need no data: idle level, MISO and IO release, CS timing and whole bytes on writes. A strict flash model refuses what the datasheet forbids: programs without WEL, quad reads with QE clear, commands while BUSY. A scoreboard compares readback with a reference memory. Bugs escape through a lenient model, page-wrap writes, off-by-one dummy counts and turnaround timing.
The Bug-Hunt BenchStimulus programs drive the controller; the flash answers; the checker watches the enables; each program reads its result back. Illustrative sequence- The wire eye
The checker reads both enables on every clock. It catches a fight for the lanes and nothing else.
- The readback eye
Each program knows what the flash should hold and reads it back. It catches what the flash did, legal wire or not.
- The record
The flash prints a line per command. It rules on nothing; it is the evidence the other two eyes point at.
Read the diagram as text
- Stimulus programs: seven tasks
- Controller: six faults
- Flash model: five faults
- Contention checker: ctrl_oe & flash_oe
- Readback: data ok or WRONG
- Flash trace line: command, clocks, bytes
- Stimulus programs → Controller: task calls
- Controller → Flash model: pins
- Controller → Contention checker: ctrl_oe
- Flash model → Contention checker: flash_oe
- Flash model → Flash trace line
- Stimulus programs → Readback: expected bytes
Arrows are calls, pins and the values each observer reads.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names the parts of the bench: a wire monitor, wire checks, a flash model and a readback scoreboard.
What Interviewers Listen For (Senior)
A good senior answer insists the flash model is tested with stimulus the datasheet forbids. It builds a matrix of faults against test programs and covers mode, lane width, command and boundary.
- The wire eye
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Prove ItSolve P7.10.1: Check the Controller and Its Flash ModelSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Prove ItShowing the Flash Bench Catches Each FaultL2 Mid-LevelL3 Senior
Prove it: how do you show that your QSPI bench catches each class of fault, not just that the tests pass?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Plant one fault per class, such as a missing WEL, a late IO release or a page-wrap error. Run every test against every fault and record which check fires. A fault with no mark is a hole, so add a program for it. On the lesson bench the wire checker caught 1 fault of 11, and readbacks caught the rest.
Self-Check
Tick each key point you covered in your answer.
Tool as Truth
"The wire checker is clean, so the controller is right."
Most flash faults keep the wires legal. Only a readback against the datasheet rule shows what the flash did.
Source Lesson P7.10 key points
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Prove ItSolve P7.8.2: The Program That Crossed a PageSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"The extra 44 bytes spill into the next page."
The page address bits stay fixed, and only the low byte wraps. In the twin, a driver that expects the spill reads back 88 wrong bytes. Address 100h holds 55h, and the next page is still FFh.
Run It
One 300-byte Page Program wraps inside the page. Splitting it at the page boundary into two programs reads back correctly.
FAIL: 88 bytes wrong; 100h=55 12bh=55 200h=ff 22bh=ffSee the Fix
`timescale 1ns/1ps
// A driver writes 300 bytes (256 of AAh, then 44 of 55h) to 0x000100, a page start, and checks a
// readback that assumes the data lands linearly from 0x100 to 0x22B. The flash model follows
// W25Q128JV §8.2.13: within one Page Program, A7-A0 wrap inside the page. SPLIT = 1: the driver splits at the page boundary into two programs.
module tb;
localparam bit SPLIT = 1;
reg [7:0] flash [0:1023];
int bad = 0;
task automatic page_program(input [23:0] addr, input int first, input int n);
for (int i = 0; i < n; i++)
flash[{addr[23:8], 8'(addr[7:0] + i)}] = (first + i < 256) ? 8'haa : 8'h55;
endtask
initial begin
for (int a = 0; a < 1024; a++) flash[a] = 8'hff;
if (SPLIT) begin page_program(24'h000100, 0, 256); page_program(24'h000200, 256, 44); end
else page_program(24'h000100, 0, 300);
for (int i = 0; i < 300; i++) if (flash[24'h000100 + i] !== ((i < 256) ? 8'haa : 8'h55)) bad++;
if (bad == 0) $display("PASS: 300 bytes read back from 100h to 22bh");
else $display("FAIL: %0d bytes wrong; 100h=%h 12bh=%h 200h=%h 22bh=%h", bad, flash['h100], flash['h12b], flash['h200], flash['h22b]);
$finish;
end
endmodule
Prints: PASS: 300 bytes read back from 100h to 22bh
Misconception
"One Write Enable at the start covers a multi-page write."
The flash clears WEL when each Page Program finishes. So without a fresh 06h, the second program is ignored.
Source Winbond W25Q128JV datasheet Rev. F §7.1.2 Write Enable Latch (WEL); §8.2.1 Write Enable (06h); §8.2.13 Page Program (02h)
Missed Corner
"The data ends wherever CS goes high."
For program and erase, CS must rise after the eighth bit of the last byte. If it rises mid-byte, the instruction does not run at all.
Source Winbond W25Q128JV datasheet Rev. F §8.2.13 Page Program (02h)