Sharing MISO Between Peripherals

Where the interviewer goes next. Open a node to practise that follow-up.

What IfProve ItCompareScale It

1. Sharing MISO Between Peripherals
2. CompareSeparate Selects or a Daisy ChainL1 JuniorL2 Mid-Level

   Compare one chip select per device with a daisy chain.

   Reveal the Model Answer

   Separate selects cost one pin per device, but let you talk to any device alone, at its own mode and length. A daisy chain uses one select, and each device's output feeds the next device's input. So the chain is one long shift register, and every update shifts through every device. One broken device breaks the chain, and every device must support pass-through. It suits strings of identical parts, such as LED drivers or shift registers.

   1. One 24-clock frame

      The first byte sent travels furthest: after 24 clocks 11h sits in p2, 22h in p1, 33h in p0.

   2. What comes back

      Meanwhile the old contents shift out of p2 into the controller, oldest first.

   Read the diagram as text

   • Controller: sends 11h, 22h, 33h
   • p0: ends up with 33h
   • p1: ends up with 22h
   • p2: ends up with 11h
   • MISO: last device to controller

   • Controller → p0: MOSI
   • p0 → p1: q0
   • p1 → p2: q1
   • p2 → MISO
   • MISO → Controller

   Arrows are the path of the bits. Measured: p0 33, p1 22, p2 11.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Separate selects cost one pin per device, but let you talk to any device alone, at its own mode and length. Key point 2 A daisy chain uses one select, and each device's output feeds the next device's input. Key point 3 So the chain is one long shift register, and every update shifts through every device. Key point 4 One broken device breaks the chain, and every device must support pass-through. Key point 5 It suits strings of identical parts, such as LED drivers or shift registers.

   What Interviewers Listen For (Junior)

   A good junior answer weighs the pin count against being able to reach each device alone.

   • Lesson P7.4Many Peripherals: CS, Daisy Chain and Tri-State
   • Problem P7.4.2Load Three Devices Through One Chain
3. Prove ItSolve P7.4.2: Load Three Devices Through One ChainSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P7.4.2

4. What IfSwitching from One Device to the NextL2 Mid-Level

   How soon after one select rises may the controller select another device and read it?

   Reveal the Model Answer

   The first device needs its output-disable time to let go of MISO: 7 ns maximum (tSHQZ) on the W25Q128JV. The next device's first driven bit must come later than that. The same device also has its own minimum deselect time before it accepts a new command. On that flash it is 10 ns after a read and 50 ns after a program, erase or write.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The first device needs its output-disable time to let go of MISO: 7 ns maximum (tSHQZ) on the W25Q128JV. Key point 2 The next device's first driven bit must come later than that. Key point 3 The same device also has its own minimum deselect time before it accepts a new command. Key point 4 On that flash it is 10 ns after a read and 50 ns after a program, erase or write.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer names two limits. One is the old device's output-disable time; the other is a device's minimum deselect time.

   • Lesson P7.4Many Peripherals: CS, Daisy Chain and Tri-State
   • Lesson P7.3Timing: Setup, Hold and the Half-Cycle Budget
5. Scale ItVerifying an SPI Flash ControllerL2 Mid-LevelL3 Senior

   You verify a QSPI flash controller that does reads, page programs and erases. What is in your bench, and which bugs would still escape?

   Reveal the Model Answer

   Use a wire monitor for every supported mode and lane width. Add wire checks that need no data: idle level, MISO and IO release, CS timing and whole bytes on writes. A strict flash model refuses what the datasheet forbids: programs without WEL, quad reads with QE clear, commands while BUSY. A scoreboard compares readback with a reference memory. Bugs escape through a lenient model, page-wrap writes, off-by-one dummy counts and turnaround timing.

   1. The wire eye

      The checker reads both enables on every clock. It catches a fight for the lanes and nothing else.

   2. The readback eye

      Each program knows what the flash should hold and reads it back. It catches what the flash did, legal wire or not.

   3. The record

      The flash prints a line per command. It rules on nothing; it is the evidence the other two eyes point at.

   Read the diagram as text

   • Stimulus programs: seven tasks
   • Controller: six faults
   • Flash model: five faults
   • Contention checker: ctrl_oe & flash_oe
   • Readback: data ok or WRONG
   • Flash trace line: command, clocks, bytes

   • Stimulus programs → Controller: task calls
   • Controller → Flash model: pins
   • Controller → Contention checker: ctrl_oe
   • Flash model → Contention checker: flash_oe
   • Flash model → Flash trace line
   • Stimulus programs → Readback: expected bytes

   Arrows are calls, pins and the values each observer reads.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Use a wire monitor for every supported mode and lane width. Key point 2 Add wire checks that need no data: idle level, MISO and IO release, CS timing and whole bytes on writes. Key point 3 A strict flash model refuses what the datasheet forbids: programs without WEL, quad reads with QE clear, commands while BUSY. Key point 4 A scoreboard compares readback with a reference memory. Key point 5 Bugs escape through a lenient model, page-wrap writes, off-by-one dummy counts and turnaround timing.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer names the parts of the bench: a wire monitor, wire checks, a flash model and a readback scoreboard.

   • Lesson P7.5The SPI Monitor and Checker
   • Lesson P7.10Capstone: A QSPI Controller and Flash Bug Hunt
   • Lesson P7.14Power-Up, Pin Timing and DC Levels
   • Problem P7.10.1Check the Controller and Its Flash Model
   • Problem P7.10.2Choose Flash Programs That Expose Hidden Faults
6. Prove ItSolve P7.10.1: Check the Controller and Its Flash ModelSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P7.10.1

7. Prove ItShowing the Flash Bench Catches Each FaultL2 Mid-LevelL3 Senior

   Prove it: how do you show that your QSPI bench catches each class of fault, not just that the tests pass?

   Reveal the Model Answer

   Plant one fault per class, such as a missing WEL, a late IO release or a page-wrap error. Run every test against every fault and record which check fires. A fault with no mark is a hole, so add a program for it. On the lesson bench the wire checker caught 1 fault of 11, and readbacks caught the rest.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Plant one fault per class, such as a missing WEL, a late IO release or a page-wrap error. Key point 2 Run every test against every fault and record which check fires. Key point 3 A fault with no mark is a hole, so add a program for it. Key point 4 On the lesson bench the wire checker caught 1 fault of 11, and readbacks caught the rest.

   Tool as Truth

   "The wire checker is clean, so the controller is right."

   Most flash faults keep the wires legal. Only a readback against the datasheet rule shows what the flash did.

   Source Lesson P7.10 key points

   • Lesson P7.10Capstone: A QSPI Controller and Flash Bug Hunt
   • Problem P7.10.1Check the Controller and Its Flash Model
8. Prove ItSolve P7.4.1: Release MISO When DeselectedSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P7.4.1