Interview Question · Debug
The Reply Shifted by One Bit
The Question
The interviewer asks
Your controller reads a peripheral's ID register as 52h, but the datasheet says A5h. Writes seem to work. What is your first suspect?
Illustrative peripheral-ID read
Expected ID: A5h
Received ID: 52h
Write transactions appear to succeedYou have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A clean one-bit shift is the signature of an SPI mode mismatch, not noise. Both sides move one bit per clock but disagree on which edge carries it. The controller samples each bit just before the peripheral launches it, so it gets the previous bit. The lost bit turns up in the next byte. With a mode-0 controller and a mode-1 peripheral, writes can still pass. But their only hold time is the launch delay.
- Cycle 2
The controller samples MISO on this rising edge. The peripheral launches on it too, 1 ns later.
- Cycle 18
Second byte: every bit the controller takes is the bit before. Bit 7 of the echo is late, and so is every bit after it.
Measured: two loopback bytes of A5h. The controller reads the second as 52h, one bit late. The peripheral still gets A5h, with only 1 ns of hold.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer sees a one-bit shift as an SPI mode mismatch. It checks CPOL and CPHA against the device datasheet.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains the race when both sides use the same edge, and checks hold margin in the other direction. It adds a monitor rule that data is stable at the sampling edge.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItScale It
- The Reply Shifted by One Bit
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WhyWhy Exactly One BitL1 Junior
Why is a mode mismatch a shift of exactly one bit, never two?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Both sides still move one bit per clock and agree on the number of clocks. They disagree only on which of the two edges in a clock period carries the bit. Those edges are half a period apart. Sampling on the launch edge reads the value from before the launch, which is the previous bit. So every bit lands exactly one place late.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer explains that both sides count the same clocks but use edges half a period apart. So the controller samples the bit before the one it wants.
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What IfPassing in Simulation, Failing on the BoardL2 Mid-Level
The mismatched direction passes in your zero-delay simulation. Why might it fail in silicon, and how do you compute the real margin?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
On the shared edge, the only hold time is the launching side's clock-to-output delay. So a model with no delays always takes the old bit and looks correct. In silicon, hold must beat the receiver's requirement, such as tCHDX of 2 ns on the W25Q128JV. For same-cycle reads, start from half a clock period. Subtract the peripheral's clock-to-output time (tCLQV) and the controller's input setup; the rest is the setup margin.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says the hold time equals the launch delay. It works out the half-period setup budget using tCLQV, the flash clock-to-output time.
What Interviewers Listen For (Senior)
A good senior answer notes that a 6 ns tCLQV breaks same-cycle sampling above about 83 MHz. The flash's rated clock does not change that.
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Prove ItSolve P7.3.1: Sample MISO After It Becomes ValidSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Break ItHow an SPI Monitor Picks Its EdgeL1 JuniorL2 Mid-Level
You write a passive SPI monitor. How does it know which edge to sample, and what can a checker on the wires assert?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
From configuration, never by guessing: rising when CPOL equals CPHA, falling otherwise. A monitor that infers the mode can be fooled by the very mismatch it should catch. On the wires alone, a checker can assert the idle clock level at CS edges and MISO released while deselected. It can also check stable data on the sample edge, whole bytes on writes and CS-to-clock times. Whether the bytes are right needs a reference model.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says the monitor takes the mode from configuration, never from guessing.
What Interviewers Listen For (Mid-Level)
A good mid-level answer lists the wire rules that need no data. It keeps them separate from checking whether the bytes are right.
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Prove ItSolve P7.5.2: Prove the SPI Sampling EdgeSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Scale ItVerifying an SPI Flash ControllerL2 Mid-LevelL3 Senior
You verify a QSPI flash controller that does reads, page programs and erases. What is in your bench, and which bugs would still escape?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Use a wire monitor for every supported mode and lane width. Add wire checks that need no data: idle level, MISO and IO release, CS timing and whole bytes on writes. A strict flash model refuses what the datasheet forbids: programs without WEL, quad reads with QE clear, commands while BUSY. A scoreboard compares readback with a reference memory. Bugs escape through a lenient model, page-wrap writes, off-by-one dummy counts and turnaround timing.
The Bug-Hunt BenchStimulus programs drive the controller; the flash answers; the checker watches the enables; each program reads its result back. Illustrative sequence- The wire eye
The checker reads both enables on every clock. It catches a fight for the lanes and nothing else.
- The readback eye
Each program knows what the flash should hold and reads it back. It catches what the flash did, legal wire or not.
- The record
The flash prints a line per command. It rules on nothing; it is the evidence the other two eyes point at.
Read the diagram as text
- Stimulus programs: seven tasks
- Controller: six faults
- Flash model: five faults
- Contention checker: ctrl_oe & flash_oe
- Readback: data ok or WRONG
- Flash trace line: command, clocks, bytes
- Stimulus programs → Controller: task calls
- Controller → Flash model: pins
- Controller → Contention checker: ctrl_oe
- Flash model → Contention checker: flash_oe
- Flash model → Flash trace line
- Stimulus programs → Readback: expected bytes
Arrows are calls, pins and the values each observer reads.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names the parts of the bench: a wire monitor, wire checks, a flash model and a readback scoreboard.
What Interviewers Listen For (Senior)
A good senior answer insists the flash model is tested with stimulus the datasheet forbids. It builds a matrix of faults against test programs and covers mode, lane width, command and boundary.
- The wire eye
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Prove ItSolve P7.10.1: Check the Controller and Its Flash ModelSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Prove ItShowing the Flash Bench Catches Each FaultL2 Mid-LevelL3 Senior
Prove it: how do you show that your QSPI bench catches each class of fault, not just that the tests pass?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Plant one fault per class, such as a missing WEL, a late IO release or a page-wrap error. Run every test against every fault and record which check fires. A fault with no mark is a hole, so add a program for it. On the lesson bench the wire checker caught 1 fault of 11, and readbacks caught the rest.
Self-Check
Tick each key point you covered in your answer.
Tool as Truth
"The wire checker is clean, so the controller is right."
Most flash faults keep the wires legal. Only a readback against the datasheet rule shows what the flash did.
Source Lesson P7.10 key points
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Prove ItSolve P7.2.2: Diagnose the Displaced SPI ReplySimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"A wrong SPI mode gives random garbage."
It gives the same bytes shifted by exactly one bit. In the twin, a mode-1 peripheral sampled on its own launch edge returns 52h 9Eh for A5h 3Ch. The bit lost from A5h reappears at the top of the next byte.
Run It
A mode-1 peripheral read by a mode-0 controller: every bit one place late, not noise. The fixed run puts the peripheral in mode 0.
FAIL: sent a5 3c, controller got 52 9eSee the Fix
`timescale 1ns/1ps
// A mode-0 controller (CPOL 0, CPHA 0: samples MISO on rising SCLK) reads two bytes from a
// peripheral holding A5h then 3Ch. Peripheral CPHA = 0: mode 0, bit 7 is out when CS falls and each later bit is launched on a falling edge.
module periph #(parameter bit CPHA = 0) (input sclk, input cs_n, output reg miso);
reg [15:0] sr = 16'ha53c;
initial miso = 0;
always @(negedge cs_n) if (!CPHA) begin miso = sr[15]; sr = sr << 1; end
always @(negedge sclk) if (!cs_n && !CPHA) begin miso <= sr[15]; sr <= sr << 1; end
always @(posedge sclk) if (!cs_n && CPHA) begin miso <= #1 sr[15]; sr <= sr << 1; end
endmodule
module tb;
reg sclk = 0, cs_n = 1;
wire miso;
reg [15:0] rx;
periph #(.CPHA(0)) p(sclk, cs_n, miso);
always @(posedge sclk) rx <= {rx[14:0], miso};
initial begin
#10 cs_n = 0; #5;
repeat (16) begin #5 sclk = 1; #5 sclk = 0; end
#5 cs_n = 1;
if (rx == 16'ha53c) $display("PASS: controller got a5 3c");
else $display("FAIL: sent a5 3c, controller got %h %h", rx[15:8], rx[7:0]);
$finish;
end
endmodule
Prints: PASS: controller got a5 3c
Misconception
"It is a bit-order bug: the peripheral sends LSB first."
A5h is 1010 0101, and that pattern reversed is the same. So a bit-order swap would still read A5h. The value 52h is A5h moved one place right, and only an edge disagreement explains that.
Source Arithmetic (1010 0101 reversed is 1010 0101); ASIC Point lesson P7.2 (measured: controller 0, peripheral 1 reads A5h as 52h)
Half-Truth
"The writes work, so the peripheral mode must be right."
In the mismatched pair, the peripheral still received A5h on the bench. But it had only 1 ns of hold, half the 2 ns data-in hold time (tCHDX) a W25Q128JV needs. It passes in simulation and fails on a board.