Interview Question · Waveform
Who Drives the Lanes in EBh
The Question
The interviewer asks
Walk me through a Fast Read Quad I/O (EBh) on a W25Q128JV, clock by clock. Who drives IO0 to IO3 at each point?
/CS low
Phase: opcode EBh | 24-bit address | mode byte | dummy clocks | data
Fill in: clock count, lane count and IO0-IO3 owner for each phase.
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Reveal the Model Answer
The controller sends EBh on IO0 alone for 8 clocks. Then it sends the 24-bit address on all four lanes in 6 clocks, and the mode byte in 2 more. Then come 4 dummy clocks, in which the controller must release the lanes. From clock 20 the flash drives one byte every 2 clocks, high nibble first, with the top bit on IO3. QE in status register 2 must be set, because IO2 and IO3 replace the /WP and /HOLD pins.
Read phases and sample points (half clock)
- command: columns 1 through 16.
- address: columns 17 through 28.
- mode: columns 29 through 32.
- dummy: columns 33 through 40.
- data: columns 41 through 48.
- Cycle 1
The instruction goes out on IO0 alone: ctrl_oe is 0001.
- Cycle 17
From the address on, the controller drives all four lanes: ctrl_oe is 1111.
- Cycle 33
The turnaround. Both enables are 0 and the lanes float. The controller has let go; the flash has not started.
- Cycle 41
The flash drives from the falling edge after the last dummy clock: flash_oe is 1111.
Generated from the transaction and decoded back. The two enable lanes never have a 1 in the same position: the bench's clean run prints no contention line.
| Clocks | Phase | Lanes | Driven by |
|---|---|---|---|
| 0-7 | Instruction EBh | IO0 | Controller |
| 8-13 | Address A23-A0 | IO0-IO3, 4 bits per clock | Controller |
| 14-15 | Mode byte M7-M0 | IO0-IO3 | Controller |
| 16-19 | Dummy | IO0-IO3 | Nobody: turnaround |
| 20 on | Data, 2 clocks per byte | IO0-IO3 | Flash |
One byte costs 22 clocks; a 32-byte line costs 8 + 6 + 2 + 4 + 64 = 84.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer gets the phase lengths and lane counts right. It names the handover in the dummy clocks and the need to set QE.
What Interviewers Listen For (Senior)
A good senior answer computes the cost of a cache-line miss. It knows burst wrap reorders the bytes but does not shorten the read. It predicts that one dummy clock too few shifts every nibble.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItScale It
- Who Drives the Lanes in EBh
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WhyWhy Dummy Clocks ExistL1 JuniorL2 Mid-Level
Read Data (03h) has no dummy clocks. Why do the fast reads add them?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The flash needs time to fetch the first byte after the last address bit. Read Data (03h) gets that time by running slowly: on the W25Q128JV it is limited to 50 MHz. Fast Read (0Bh) adds eight dummy clocks so the whole frame can run at the full rated clock. That is 133 MHz in the 3.0 to 3.6 V range. The quad I/O read sends the mode byte and then only four dummy clocks.
0Bh Fast Read: Eight Dummy Clocks Before the DataThe same frame as 03h with eight clocks between the address and the data, in which nobody drives. All cyclesRead phases and sample points (half clock)
- command: columns 1 through 16.
- address: columns 17 through 64.
- dummy: columns 65 through 80.
- data: columns 81 through 96.
- Cycle 65
Eight dummy clocks. The controller has released IO0 and the flash has not started: both lines float.
- Cycle 81
The first data bit, launched on the falling edge after the eighth dummy clock.
Generated and decoded back; the bench measured QSPI 0b 001014 M -- C48 B1.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says the flash needs time to fetch the first byte.
What Interviewers Listen For (Mid-Level)
A good mid-level answer quotes the slower Read Data clock against the full Fast Read clock. It explains the trade between dummy clocks and clock speed.
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What IfToo Few Dummy Clocks on a Fast ReadL1 JuniorL2 Mid-Level
What if the controller sends six dummy clocks instead of eight for Fast Read (0Bh)?
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Reveal the Model Answer
The flash drives data only after its eighth dummy clock. The controller starts sampling two clocks early, so it reads two junk bits first. Every byte it returns is then shifted by two bits. Check the dummy count per command, because the quad reads use different counts.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Dummy clocks are just padding, so any count works."
The flash counts them to know when to drive data. A different count shifts every byte the controller reads.
Source Winbond W25Q128JV datasheet Rev. F §8.2.7 Fast Read (0Bh)
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What IfReleasing the Quad Lanes LateL2 Mid-Level
The controller releases IO0 to IO3 one clock late, after the first data clock. What do you see, and how would your bench catch it?
log Illustrative quad-data turnaround excerpt Dummy phase ends First data clock: flash drives IO0-IO3 Controller still drives IO0-IO3 Next clock: controller releases IO0-IO32:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Both drivers are on during the first data clock. Simulation shows x on lanes where they disagree; the board shows mid-rail levels and wrong bits. A bench catches it with a wire rule: no lane has two drivers. Or it checks that the controller's output enables are off before the first data clock. Waiting for a data mismatch is not enough, because matching bits hide the fight.
The Controller Still Drives When the Flash StartsEBh at 0x001014 with ctrl.drive_through_turnaround = 1: the controller turns its enables back on for the data phase. All cycles- Cycle 17
Address and mode: the controller drives all four lanes, the flash listens.
- Cycle 33
Four dummy clocks with both enables off. This is where the lanes change hands.
- Cycle 41
The flash starts driving the data, and the controller drives too. Where their bits disagree the lane is x.
Measured on the bench. The controller drives again in the data phase, so every lane where the two drivers disagree is x.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names the fight on the lanes in the first data clocks. It checks the output enables directly, not just the data.
- Cycle 17
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Prove ItSolve P7.7.1: Release the Quad Lanes at TurnaroundSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Scale ItThe Cost of an XIP Cache MissL2 Mid-LevelL3 Senior
A CPU executes in place from this flash with a 32-byte cache line. What does one miss cost, and does burst wrap make it cheaper?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
One EBh read of the line: 8 instruction, 6 address, 2 mode, 4 dummy and 64 data clocks, 84 in all. Burst wrap, set with 77h, does not reduce that. It starts at the byte that missed and wraps within the aligned section. So the CPU can resume while the rest of the line streams in.
EBh at 0x001014 with 32-byte WrapThe flash starts at the requested byte and wraps to the start of its aligned 32-byte section. All cyclesRead phases and sample points (half clock)
- command: columns 1 through 16.
- address: columns 17 through 28.
- mode: columns 29 through 32.
- dummy: columns 33 through 40.
- data: columns 41 through 96.
- Cycle 41
The first byte is the one the CPU wanted: 0x14.
- Cycle 85
0x1f is the last byte of the section 0x001000 to 0x00101f.
- Cycle 89
The flash wraps to 0x00 and goes on until CS rises, never leaving the section.
Generated from the measured byte order (the first 14 of 32 bytes) and decoded back.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer adds up the clocks correctly: 84 for one cache line.
What Interviewers Listen For (Senior)
A good senior answer separates the wait for the first needed byte from the total cost. It weighs burst wrap against line size and controller support.
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Prove ItSolve P7.9.2: A Cache Line in Eighty-Four ClocksSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Prove ItSolve P7.6.1: Decode the Flash Read PhasesSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"In quad mode the instruction goes out on all four lanes too."
Not for EBh, which is 1-4-4. The instruction byte goes on IO0 for 8 clocks; only the address, mode and data use four lanes. Four lanes for the instruction is QPI, which is 4-4-4.
Source Winbond W25Q128JV datasheet Rev. F §8.2.11 Fast Read Quad I/O (EBh), Figure 24a; §8.1.3 Instruction Set Table 2 (Number of Clock 1-4-4)
Missed Corner
"Dummy clocks are idle time; nothing happens on the pins."
The lanes change direction there. The controller must release them before the flash starts driving. Otherwise both drive at once: x in simulation, and wrong bits and extra current on a board.
Source Winbond W25Q128JV datasheet Rev. F §8.2.11 Figure 24a (IOs switch from input to output after the dummy clocks); §8.2.9 (IO pins high impedance before the falling edge of the first data-out clock)
Missed Corner
"One dummy clock too few just costs one bad bit."
The controller samples one clock early for the whole frame. So every nibble lands one place late, and the first sampled nibble is undriven. Every byte is wrong.
Source ASIC Point lesson P7.6 (measured EBh twin on Icarus Verilog 12: nibble shift with one dummy clock too few)