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Interview Question · Concept

The Baud Mismatch Budget

L1 JuniorL2 Mid-Leveluartbaud rate

The Question

The interviewer asks

Your UART and its peer run from different clocks. How much baud-rate mismatch can the link tolerate, and which bit fails first?

Reveal the Model Answer

Drift is zero at each start edge and grows with every bit. So the last sample, the stop bit, fails first. A receiver that samples exact bit centres has half a bit of slack over the nine bits before the stop. That is about ±5.6 %, shared by both ends. Real receivers do worse: the site's bench receiver first loses 8N1 frames at +4.5 % and −6 %. The 8E1 format fails earlier, because parity puts the stop bit one bit later.

Measured sweepFrames Decoded Against Rate Error, Back to Back64 seeded frames per 0.5 % step, frames back to back, the bench receiver. Positive error is a slower transmitter.
  • 8N1
  • 8E1
  • 8N2
0102030405060Frames decoded of 64-8%-6%-4%-2%02%4%6%8%Transmitter rate error8N1 −6 %8N1 +4.5 %0204060Frames decoded of 64-5%05%Transmitter rate error8N1 −6 %8N1 +4.5 %
Read the plot as a table
Transmitter rate error8N18E18N2
-8%009
-6%0064
-4%646464
-2%646464
0%646464
2%646464
4%645264
6%745
8%012

Measured, 64 frames per step, back to back. 8N1 first loses frames at −6 % and at +4.5 %, and 8E1 fails one step earlier on both sides.

Where the Budget GoesArrows read as "leads to". A slow transmitter moves the samples toward the start of each bit, a fast one toward the end.
Where the budget goesArrows read as "leads to". A slow transmitter moves the samples toward the start of each bit, a fast one toward the end. component Rate error e TX bit = 16 × (1 + e)ticks component Drift 16·e·k ticks atsample k component Stop sample largest k, drifts most component Slow side, e > 0 room to the start ofthe bit component Fast side, e < 0 room to the end ofthe bit early samplelate sample
Read the diagram as text
  • Rate error e: TX bit = 16 × (1 + e) ticks
  • Drift: 16·e·k ticks at sample k
  • Stop sample: largest k, drifts most
  • Slow side, e > 0: room to the start of the bit
  • Fast side, e < 0: room to the end of the bit
  • Rate error e → Drift
  • Drift → Stop sample
  • Stop sample → Slow side, e > 0: early sample
  • Stop sample → Fast side, e < 0: late sample

The budget is about half a bit spread over the frame, split by where the sample sits.

  1. Drift

    A transmitter bit longer by a fraction e ends 16·e·k ticks late at bit k. The stop bit has the largest k.

  2. Slow side

    The stop bit starts at 144·(1 + e) ticks; the centre sample is at 152. It reads data 7 once e passes 8/144, about 5.6 %.

  3. Fast side

    Data 7 ends at 144·(1 + e); its sample is at 136. Past about −5.6 % it reads the stop bit: wrong data, and with an idle line after, no flag.

  4. Both ends

    Divisor rounding plus the peer's oscillator: 115200 from 50 MHz with divisor 27 is already +0.47 %.

RUNIcarus Verilog · in your browser
Edit the code, then run it
Expected: e = +4.5 %: RX 55 ok e = +5.5 %: RX 55 ok e = +6.0 %: RX 55 FE e = -5.5 %: RX 55 ok e = -6.0 %: RX d5 ok

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Junior)

A good junior answer says the stop bit fails first because drift grows from the start edge. It says both ends share a budget of roughly 5 %.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItScale It

  1. The Baud Mismatch Budget
  2. WhyWhy the Stop Bit Fails FirstL1 Junior

    Why is it the stop bit that fails, and not data bit 0?

    Reveal the Model Answer

    The start edge is the only moment both ends agree on, and drift is zero there. Each later bit adds the same timing error. So the sample furthest from the start edge, the stop sample, has drifted most. This is also why the receiver restarts its count on every start edge. The error never carries from one frame to the next.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer says drift grows evenly from the start edge and resets with every new frame.

  3. What IfDoes a Second Stop Bit HelpL2 Mid-Level

    Would switching to two stop bits give you more tolerance?

    Reveal the Model Answer

    It helps only on the fast side, and only when frames stream back to back. There, with a fast transmitter, the stop sample comes late and can land in the next start bit. It then reads 0. A second stop bit puts idle time there instead. With idle time between frames it buys nothing: the P6.4 sweep shows 8N1 and 8N2 failing at the same steps.

    Measured sweepThe Same Sweep with an Idle Bit Between FramesOne idle bit plus a seeded fraction of a tick before every frame. Compare 8N1 and 8N2 on the fast side.
    • 8N1
    • 8E1
    • 8N2
    0102030405060Frames decoded of 64-8%-6%-4%-2%02%4%6%8%Transmitter rate error8N1 −6.5 %8N1 +4.5 %0204060Frames decoded of 64-5%05%Transmitter rate error8N1 −6.5 %8N1 +4.5 %
    Read the plot as a table
    Transmitter rate error8N18E18N2
    -8%959
    -6%644364
    -4%646464
    -2%646464
    0%646464
    2%646464
    4%644864
    6%547
    8%202

    Measured with an idle bit between frames. 8N1 and 8N2 first lose frames at the same steps, −6.5 % and +4.5 %.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer says a second stop bit helps only on the fast side, with frames back to back. It cites the measured sweep: with idle gaps there is no gain.

  4. Scale ItSigning off a UART Link BudgetL2 Mid-LevelL3 Senior

    Your SoC talks to a module clocked by an RC oscillator. How do you sign off that the UART link works across temperature and parts?

    Reveal the Model Answer

    Add up the error sources: this end's divisor rounding and clock tolerance, and the peer's oscillator tolerance over temperature and voltage. Compare the sum, in both directions, with the receiver's measured budget for the frame format in use, not a quoted 5 %. In simulation, sweep the peer rate in fine steps, both ways, in every supported format. Run frames back to back and with gaps. Record the first failing step as the sign-off number.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer adds up the errors of both ends. It compares them with the budget for the frame format really in use.

  5. WhyWhy the Baud Budget Is LopsidedL2 Mid-LevelL3 Senior

    Why is the measured 8N1 budget +4.5 % on one side and −6 % on the other, not ±5 %?

    Reveal the Model Answer

    A rate error moves each sample further from its bit centre, and the stop bit moves most. The total room is about half a bit over the frame. A receiver that samples a little before the centre has less room on one side and more on the other. So quote the budget with its receiver, format and pacing.

    Self-Check

    Tick each key point you covered in your answer.

    Misconception

    "Every UART tolerates ±5 %."

    The budget depends on the frame format and where the receiver samples. The lesson receiver measured +4.5 % and −6 % for 8N1.

    Source ASIC Point lesson P6.4 (measured)

  6. Prove ItSolve P6.4.1: A Receiver That Survives the SweepSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P6.4.1

What People Get Wrong

Common wrong answers and why they fail.

Missed Corner

"A rate error always shows up as a framing error."

That holds only on the slow side. A fast transmitter sends the stop bit early, so the data 7 sample reads it. If the line idles after the frame, the stop sample still reads 1. In the run, −6 % delivers D5h for 55h with no flag.

Source This question's run (Icarus Verilog 12): at −6 % it delivers D5h with no flag

Half-Truth

"Each end may be off by 5 %."

The budget belongs to the link, not to each end. Divisor rounding at one end and the peer's oscillator error add up. Real receivers also have less than the ideal ±5.6 %.

Misconception

"Adding parity makes the link more robust to clock error."

Parity makes the frame longer, so the stop sample sits one bit further from the start edge. In the P6.4 sweep, 8E1 first fails at +4 %, and 8N1 at +4.5 %.

Source ASIC Point lesson P6.4 (measured sweep): 8E1 first fails at +4 %, 8N1 at +4.5 %

Learn It, Then Prove It