Interview Question · Concept

Why a UART Oversamples

L0 FresherL1 Junioruartoversampling

The interviewer asks

Why does a UART receiver run at 16 times the baud rate? Walk me through how it finds and samples each bit.

Reveal the Model Answer

There is no clock on the wire, so a fast local clock finds the start edge to within one tick. It then counts to the middle of every bit. A typical receiver rejects glitches in the middle of the start bit. There, 8 ticks after the edge, the line must still be low. After that it samples every 16 ticks, often with a 2-of-3 vote over ticks. At 16x a sample is off by at most a sixteenth of a bit; at 2x, by half a bit.

The Sixteen-Tick ReceiverArrows show data moving from the wire to the holding register. Every box runs on the receiver's own tick clock.

Find the start
The low-run counter resets on every high tick. Eight lows in a row mean a start bit, and that tick is the middle of it.
Count to each middle
From the start, the bit counter fires every 16 ticks: the middle of data 0, data 1 and so on to the stop bit.
Sample and deliver
Each sample is a vote of three ticks. After the stop sample the byte and its flags go to the holding register.

Read the diagram as text

rx wire: no clock with it
Low-run counter: counts consecutive low ticks
Start check: 8 low ticks: a start
Bit counter: every 16th tick: a sample
Vote: 2 of the 3 ticks ending on the sample
Shift register: data bits, then stop
Holding register: data, valid, flags

rx wire → Low-run counter
Low-run counter → Start check: 8
Start check → Bit counter: go
Bit counter → Vote: sample now
Vote → Shift register: bit
Shift register → Holding register: after stop

Finding the start and finding the middle are one counter: eight ticks.

Measured sweepOne Sample per Bit Against SixteenThe same 64 seeded frames at each rate error, on one wire, into two receivers.

one sample per bit
sixteen per bit (rx0)

Read the plot as a table

Transmitter rate error	one sample per bit	sixteen per bit (rx0)
-3%	46	64
-2%	55	64
-1%	60	64
0%	64	64
1%	56	64
2%	55	64
3%	54	64

Measured. With one sample per bit, the receiver keeps only 46 of 64 frames at −3 %. The sixteen-tick receiver decodes all 64 at every step shown.

Hunt
Wait for a falling edge on the idle line.
Confirm
Eight ticks later, mid start bit, is the line still low? If not, it was a glitch: go back to hunting.
Sample
Every 16 ticks after that: data 0 at tick 24, data 7 at tick 136, the stop bit at tick 152.
Check and deliver
Stop sample 1: deliver the byte. Stop sample 0: framing error. Then hunt again; drift restarts at zero on the next edge.

Self-Check

Tick each key point you covered in your answer.

Key point 1 There is no clock on the wire, so a fast local clock finds the start edge to within one tick. Key point 2 It then counts to the middle of every bit. Key point 3 A typical receiver rejects glitches in the middle of the start bit. Key point 4 There, 8 ticks after the edge, the line must still be low. Key point 5 After that it samples every 16 ticks, often with a 2-of-3 vote over ticks. Key point 6 At 16x a sample is off by at most a sixteenth of a bit; at 2x, by half a bit.

What Interviewers Listen For (Fresher)

A good fresher answer says there is no clock on the wire, so the receiver samples in the middle of each bit. It uses 16 ticks per bit to find that middle.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItScale It

Why a UART Oversamples
WhyWhy 16 and Not 2L1 JuniorL2 Mid-Level
Why 16x? Would 4x or 64x be better?

Reveal the Model Answer

The ratio sets the quantisation error of finding the start edge: up to one tick, or 1/N of a bit. At 2x that is half a bit, which already uses the whole budget; at 16x it is about 6 %. Beyond that, the rate mismatch between the two clocks dominates. So 64x buys little and costs a faster clock and wider counters. Sixteen also leaves room for a centred vote over several ticks.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The ratio sets the quantisation error of finding the start edge: up to one tick, or 1/N of a bit. Key point 2 At 2x that is half a bit, which already uses the whole budget; at 16x it is about 6 %. Key point 3 Beyond that, the rate mismatch between the two clocks dominates. Key point 4 So 64x buys little and costs a faster clock and wider counters. Key point 5 Sixteen also leaves room for a centred vote over several ticks.

What Interviewers Listen For (Junior)
A good junior answer says the start edge is found to within one tick. That error is 1/N of a bit.
- Lesson P6.3The Receiver: Oversampling and the Sample Point
- Lesson P6.4Baud Mismatch: The Measured Budget
Break ItBeating the Majority VoteL1 JuniorL2 Mid-Level
Design the shortest glitch that corrupts a byte despite a 2-of-3 vote. How would your testbench inject it?

Reveal the Model Answer

Two low ticks on two of the three vote ticks of one sample win the vote. One tick never does. The bench must time the glitch against the receiver's own sample ticks. A random glitch time rarely lands on two vote ticks, so the bench must know or sweep the sample position. The P6.5 bench did this and turned 55h into 45h with no flag.
A 1-tick low on the sample tick of data 4
Measured, one column per tick for 0x55. Ticks 86 and 87 count two 1s; tick 88 reads 0 and is the sample tick. Two of three is a 1, and the counter restarts at 16.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Two low ticks on two of the three vote ticks of one sample win the vote. Key point 2 One tick never does. Key point 3 The bench must time the glitch against the receiver's own sample ticks. Key point 4 A random glitch time rarely lands on two vote ticks, so the bench must know or sweep the sample position. Key point 5 The P6.5 bench did this and turned 55h into 45h with no flag.

What Interviewers Listen For (Junior)
A good junior answer says a glitch must cover two of the three vote ticks to change a bit.
- Lesson P6.5Errors, Break and Recovery
- Problem P6.6.2A Compact UART Voter and Sampler
Prove ItSolve P6.6.2: A Compact UART Voter and SamplerSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem P6.6.2
What IfThe Baud Mismatch BudgetL1 JuniorL2 Mid-Level
Asked if they assume both clocks are exact

Your UART and its peer run from different clocks. How much baud-rate mismatch can the link tolerate, and which bit fails first?
2:30

You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.

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Reveal the Model Answer

Drift is zero at each start edge and grows with every bit. So the last sample, the stop bit, fails first. A receiver that samples exact bit centres has half a bit of slack over the nine bits before the stop. That is about ±5.6 %, shared by both ends. Real receivers do worse: the site's bench receiver first loses 8N1 frames at +4.5 % and −6 %. The 8E1 format fails earlier, because parity puts the stop bit one bit later.

Measured sweepFrames Decoded Against Rate Error, Back to Back64 seeded frames per 0.5 % step, frames back to back, the bench receiver. Positive error is a slower transmitter.

8N1
8E1
8N2

Read the plot as a table
Transmitter rate error 8N1 8E1 8N2
-8% 0 0 9
-6% 0 0 64
-4% 64 64 64
-2% 64 64 64
0% 64 64 64
2% 64 64 64
4% 64 52 64
6% 7 4 5
8% 0 1 2

Measured, 64 frames per step, back to back. 8N1 first loses frames at −6 % and at +4.5 %, and 8E1 fails one step earlier on both sides.

Where the Budget GoesArrows read as "leads to". A slow transmitter moves the samples toward the start of each bit, a fast one toward the end.

Read the diagram as text
Rate error e: TX bit = 16 × (1 + e) ticks
Drift: 16·e·k ticks at sample k
Stop sample: largest k, drifts most
Slow side, e > 0: room to the start of the bit
Fast side, e < 0: room to the end of the bit
Rate error e → Drift
Drift → Stop sample
Stop sample → Slow side, e > 0: early sample
Stop sample → Fast side, e < 0: late sample

The budget is about half a bit spread over the frame, split by where the sample sits.

Drift
A transmitter bit longer by a fraction e ends 16·e·k ticks late at bit k. The stop bit has the largest k.
Slow side
The stop bit starts at 144·(1 + e) ticks; the centre sample is at 152. It reads data 7 once e passes 8/144, about 5.6 %.
Fast side
Data 7 ends at 144·(1 + e); its sample is at 136. Past about −5.6 % it reads the stop bit: wrong data, and with an idle line after, no flag.
Both ends
Divisor rounding plus the peer's oscillator: 115200 from 50 MHz with divisor 27 is already +0.47 %.

RUNIcarus Verilog · in your browser

Edit the code, then run it

Expected: e = +4.5 %: RX 55 ok e = +5.5 %: RX 55 ok e = +6.0 %: RX 55 FE e = -5.5 %: RX 55 ok e = -6.0 %: RX d5 ok

Self-Check
Tick each key point you covered in your answer.
Key point 1 Drift is zero at each start edge and grows with every bit. Key point 2 So the last sample, the stop bit, fails first. Key point 3 A receiver that samples exact bit centres has half a bit of slack over the nine bits before the stop. Key point 4 That is about ±5.6 %, shared by both ends. Key point 5 Real receivers do worse: the site's bench receiver first loses 8N1 frames at +4.5 % and −6 %. Key point 6 The 8E1 format fails earlier, because parity puts the stop bit one bit later.

What Interviewers Listen For (Junior)
A good junior answer says the stop bit fails first because drift grows from the start edge. It says both ends share a budget of roughly 5 %.
Missed Corner

"A rate error always shows up as a framing error."

That holds only on the slow side. A fast transmitter sends the stop bit early, so the data 7 sample reads it. If the line idles after the frame, the stop sample still reads 1. In the run, −6 % delivers D5h for 55h with no flag.

Source This question's run (Icarus Verilog 12): at −6 % it delivers D5h with no flag

Half-Truth

"Each end may be off by 5 %."

The budget belongs to the link, not to each end. Divisor rounding at one end and the peer's oscillator error add up. Real receivers also have less than the ideal ±5.6 %.

Misconception

"Adding parity makes the link more robust to clock error."

Parity makes the frame longer, so the stop sample sits one bit further from the start edge. In the P6.4 sweep, 8E1 first fails at +4 %, and 8N1 at +4.5 %.

Source ASIC Point lesson P6.4 (measured sweep): 8E1 first fails at +4 %, 8N1 at +4.5 %
WhyWhy the Stop Bit Fails FirstL1 Junior
Why is it the stop bit that fails, and not data bit 0?

Reveal the Model Answer

The start edge is the only moment both ends agree on, and drift is zero there. Each later bit adds the same timing error. So the sample furthest from the start edge, the stop sample, has drifted most. This is also why the receiver restarts its count on every start edge. The error never carries from one frame to the next.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The start edge is the only moment both ends agree on, and drift is zero there. Key point 2 Each later bit adds the same timing error. Key point 3 So the sample furthest from the start edge, the stop sample, has drifted most. Key point 4 This is also why the receiver restarts its count on every start edge. Key point 5 The error never carries from one frame to the next.

What Interviewers Listen For (Junior)
A good junior answer says drift grows evenly from the start edge and resets with every new frame.
- Lesson P6.4Baud Mismatch: The Measured Budget
What IfDoes a Second Stop Bit HelpL2 Mid-Level
Would switching to two stop bits give you more tolerance?
2:30

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Your level

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Reveal the Model Answer

It helps only on the fast side, and only when frames stream back to back. There, with a fast transmitter, the stop sample comes late and can land in the next start bit. It then reads 0. A second stop bit puts idle time there instead. With idle time between frames it buys nothing: the P6.4 sweep shows 8N1 and 8N2 failing at the same steps.

Measured sweepThe Same Sweep with an Idle Bit Between FramesOne idle bit plus a seeded fraction of a tick before every frame. Compare 8N1 and 8N2 on the fast side.

8N1
8E1
8N2

Read the plot as a table
Transmitter rate error 8N1 8E1 8N2
-8% 9 5 9
-6% 64 43 64
-4% 64 64 64
-2% 64 64 64
0% 64 64 64
2% 64 64 64
4% 64 48 64
6% 5 4 7
8% 2 0 2

Measured with an idle bit between frames. 8N1 and 8N2 first lose frames at the same steps, −6.5 % and +4.5 %.

Self-Check
Tick each key point you covered in your answer.
Key point 1 It helps only on the fast side, and only when frames stream back to back. Key point 2 There, with a fast transmitter, the stop sample comes late and can land in the next start bit. Key point 3 It then reads 0. Key point 4 A second stop bit puts idle time there instead. Key point 5 With idle time between frames it buys nothing: the P6.4 sweep shows 8N1 and 8N2 failing at the same steps.

What Interviewers Listen For (Mid-Level)
A good mid-level answer says a second stop bit helps only on the fast side, with frames back to back. It cites the measured sweep: with idle gaps there is no gain.
- Lesson P6.4Baud Mismatch: The Measured Budget
Scale ItSigning off a UART Link BudgetL2 Mid-LevelL3 Senior
Your SoC talks to a module clocked by an RC oscillator. How do you sign off that the UART link works across temperature and parts?

Reveal the Model Answer

Add up the error sources: this end's divisor rounding and clock tolerance, and the peer's oscillator tolerance over temperature and voltage. Compare the sum, in both directions, with the receiver's measured budget for the frame format in use, not a quoted 5 %. In simulation, sweep the peer rate in fine steps, both ways, in every supported format. Run frames back to back and with gaps. Record the first failing step as the sign-off number.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Add up the error sources: this end's divisor rounding and clock tolerance, and the peer's oscillator tolerance over temperature and voltage. Key point 2 Compare the sum, in both directions, with the receiver's measured budget for the frame format in use, not a quoted 5 %. Key point 3 In simulation, sweep the peer rate in fine steps, both ways, in every supported format. Key point 4 Run frames back to back and with gaps. Key point 5 Record the first failing step as the sign-off number.

What Interviewers Listen For (Mid-Level)
A good mid-level answer adds up the errors of both ends. It compares them with the budget for the frame format really in use.
WhyWhy the Baud Budget Is LopsidedL2 Mid-LevelL3 Senior
Why is the measured 8N1 budget +4.5 % on one side and −6 % on the other, not ±5 %?

Reveal the Model Answer

A rate error moves each sample further from its bit centre, and the stop bit moves most. The total room is about half a bit over the frame. A receiver that samples a little before the centre has less room on one side and more on the other. So quote the budget with its receiver, format and pacing.

Self-Check
Tick each key point you covered in your answer.
Key point 1 A rate error moves each sample further from its bit centre, and the stop bit moves most. Key point 2 The total room is about half a bit over the frame. Key point 3 A receiver that samples a little before the centre has less room on one side and more on the other. Key point 4 So quote the budget with its receiver, format and pacing.

Misconception

"Every UART tolerates ±5 %."

The budget depends on the frame format and where the receiver samples. The lesson receiver measured +4.5 % and −6 % for 8N1.

Source ASIC Point lesson P6.4 (measured)
- Lesson P6.4Baud Mismatch: The Measured Budget
- Problem P6.4.1A Receiver That Survives the Sweep
Prove ItSolve P6.4.1: A Receiver That Survives the SweepSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem P6.4.1
Prove ItSolve P6.3.2: Move the Sample into the BitSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem P6.3.2

Transmitter rate error	8N1	8E1	8N2
-8%	0	0	9
-6%	0	0	64
-4%	64	64	64
-2%	64	64	64
0%	64	64	64
2%	64	64	64
4%	64	52	64
6%	7	4	5
8%	0	1	2

Transmitter rate error	8N1	8E1	8N2
-8%	9	5	9
-6%	64	43	64
-4%	64	64	64
-2%	64	64	64
0%	64	64	64
2%	64	64	64
4%	64	48	64
6%	5	4	7
8%	2	0	2

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Missed Corner

"The receiver starts a frame on any falling edge."

A short glitch then starts a phantom frame. The receiver is still busy when the real start edge arrives. In the twin, a receiver that trusts the edge delivers 5Fh with a framing error, then a phantom FFh. Re-checking the line in the middle of the start bit fixes it.

Run It

An edge-only receiver turns one glitch and one 41h frame into two wrong frames. The fixed receiver re-checks the line in the middle of the start bit.

RUNIcarus Verilog · in your browser

Edit the code, then run it

Expected: t=162: RX 5f FE t=380: RX ff ok FAIL: one 41h frame sent, 2 frames delivered

`timescale 1ns/1ps
// 16 ticks (ns) per bit. A 3-tick low glitch hits the idle line at t = 10, then one clean 8N1
// frame of 41h starts at t = 100. CHECK_MID = 0: the receiver trusts the falling edge alone.
module tb;
  localparam bit CHECK_MID = 0;
  reg line = 1;
  int frames = 0; reg [7:0] d; reg stop;
  initial forever begin
    @(negedge line);
    #8;
    if (!CHECK_MID || !line) begin
      #16; for (int i = 0; i < 8; i++) begin d[i] = line; #16; end
      stop = line; frames++;
      $display("t=%0d: RX %h %s", $time, d, stop ? "ok" : "FE");
    end
  end
  initial begin
    #10 line = 0; #3 line = 1;                       // the glitch
    #87;                                             // t = 100
    line = 0; #16;
    for (int i = 0; i < 8; i++) begin line = 8'h41 >> i; #16; end
    line = 1; #400;
    if (frames == 1 && d == 8'h41 && stop) $display("PASS: one frame, 41 ok");
    else $display("FAIL: one 41h frame sent, %0d frames delivered", frames);
    $finish;
  end
endmodule

See the Fix

`timescale 1ns/1ps
// 16 ticks (ns) per bit. A 3-tick low glitch hits the idle line at t = 10, then one clean 8N1
// frame of 41h starts at t = 100. CHECK_MID = 1: the receiver re-checks that the line is still low 8 ticks after the edge, mid start bit.
module tb;
  localparam bit CHECK_MID = 1;
  reg line = 1;
  int frames = 0; reg [7:0] d; reg stop;
  initial forever begin
    @(negedge line);
    #8;
    if (!CHECK_MID || !line) begin
      #16; for (int i = 0; i < 8; i++) begin d[i] = line; #16; end
      stop = line; frames++;
      $display("t=%0d: RX %h %s", $time, d, stop ? "ok" : "FE");
    end
  end
  initial begin
    #10 line = 0; #3 line = 1;                       // the glitch
    #87;                                             // t = 100
    line = 0; #16;
    for (int i = 0; i < 8; i++) begin line = 8'h41 >> i; #16; end
    line = 1; #400;
    if (frames == 1 && d == 8'h41 && stop) $display("PASS: one frame, 41 ok");
    else $display("FAIL: one 41h frame sent, %0d frames delivered", frames);
    $finish;
  end
endmodule

Prints: t=252: RX 41 ok PASS: one frame, 41 ok

Misconception

"Sample at the bit edges, every 16 ticks from the falling edge."

An edge is exactly where the line changes. So any jitter or rate error picks the neighbouring bit. The P6.3 bench moved its sample to the edge. It decoded 55h as AAh with a framing error, even at zero rate error.

Source ASIC Point lesson P6.3 (measured): sampling at the bit edge decodes 55h as AAh with a framing error

Misconception

"The majority vote makes the receiver noise-proof."

A 2-of-3 vote outvotes a one-tick glitch. But a two-tick glitch on the right ticks wins the vote. The P6.5 bench sent 55h and delivered 45h with no flag.

Source ASIC Point lesson P6.5 (measured): a 2-tick hit on data 4 turns 55h into 45h with no flag

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Why a UART Oversamples

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What Interviewers Listen For (Fresher)

What Interviewers Listen For (Junior)

Cross-Questions

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What Interviewers Listen For (Junior)

What Interviewers Listen For (Mid-Level)

Your Answer

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What Interviewers Listen For (Junior)

What Interviewers Listen For (Mid-Level)

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What Interviewers Listen For (Mid-Level)

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What Interviewers Listen For (Senior)

Your Answer

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What People Get Wrong

Learn It, Then Prove It

Transmitter rate error	8N1	8E1	8N2
-8%	0	0	9
-6%	0	0	64
-4%	64	64	64
-2%	64	64	64
0%	64	64	64
2%	64	64	64
4%	64	52	64
6%	7	4	5
8%	0	1	2

Transmitter rate error	8N1	8E1	8N2
-8%	9	5	9
-6%	64	43	64
-4%	64	64	64
-2%	64	64	64
0%	64	64	64
2%	64	64	64
4%	64	48	64
6%	5	4	7
8%	2	0	2

Transmitter rate error	8N1	8E1	8N2
-8%	0	0	9
-6%	0	0	64
-4%	64	64	64
-2%	64	64	64
0%	64	64	64
2%	64	64	64
4%	64	52	64
6%	7	4	5
8%	0	1	2

Transmitter rate error	8N1	8E1	8N2
-8%	9	5	9
-6%	64	43	64
-4%	64	64	64
-2%	64	64	64
0%	64	64	64
2%	64	64	64
4%	64	48	64
6%	5	4	7
8%	2	0	2

The Question

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Self-Check

What Interviewers Listen For (Fresher)

What Interviewers Listen For (Junior)

Cross-Questions

Your Answer

Self-Check

What Interviewers Listen For (Junior)

What Interviewers Listen For (Mid-Level)

Your Answer

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What Interviewers Listen For (Junior)

What Interviewers Listen For (Mid-Level)

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What Interviewers Listen For (Junior)

What Interviewers Listen For (Mid-Level)

Your Answer

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What Interviewers Listen For (Junior)

Your Answer

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What Interviewers Listen For (Mid-Level)

Your Answer

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What Interviewers Listen For (Mid-Level)

What Interviewers Listen For (Senior)

Your Answer

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What People Get Wrong

Learn It, Then Prove It

Transmitter rate error	8N1	8E1	8N2
-8%	0	0	9
-6%	0	0	64
-4%	64	64	64
-2%	64	64	64
0%	64	64	64
2%	64	64	64
4%	64	52	64
6%	7	4	5
8%	0	1	2

Transmitter rate error	8N1	8E1	8N2
-8%	9	5	9
-6%	64	43	64
-4%	64	64	64
-2%	64	64	64
0%	64	64	64
2%	64	64	64
4%	64	48	64
6%	5	4	7
8%	2	0	2