Interview Question · Design
Verification Plan for a UART
- Asked at Qualcomm
The Question
The interviewer asks
You own verification of a UART IP: 16-byte FIFOs, programmable divisor, parity options and RTS/CTS. Walk me through your plan.
You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
I use three independent parts. A wire monitor reports each frame after its stop sample. A reference model predicts bytes and flags from the stimulus and the read timing, and a scoreboard compares them. Stimulus sweeps the divisor and the peer rate error both ways, in every format, back to back and with gaps. It injects faults: parity, short stop, break, glitches, slow reads and CTS toggling. Before trusting the checker, I run it against a bank of known-faulty receivers.
Read the diagram as text
- rx wire: no clock, no frame marker
- Find the start: a falling edge, low at mid-bit
- Sample each middle: one bit-time apart
- Stop sample: the frame now exists
- Byte log: UART 55 ok / FE / PE / -- BREAK
- The twin reports here: at the start edge, too early
- rx wire → Find the start
- Find the start → Sample each middle
- Sample each middle → Stop sample
- Stop sample → Byte log: report
- Find the start → The twin reports here: report
Until the stop sample there is no frame, only a candidate. The log grammar is fixed, so checkers and problems can read it.
| Feature | Stimulus | Check | Cover |
|---|---|---|---|
| Rate tolerance | Peer rate swept in 0.5 % steps, both signs | Bytes and flags match the model | Format × rate step × pacing |
| Errors | Bad parity, short stop, break, glitches | Each predicted flag, and no spurious ones | Error type × position in frame |
| FIFO and flow | Slow and bursty reads, CTS toggles | Overrun exactly when predicted; RTS at the trigger | FIFO level × CTS state |
| Recovery | A frame right after a break or an error | The next frame decodes | Error type × gap to next frame |
Rows are features from the spec; columns are what the bench does, checks and counts.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer keeps the monitor, the model and the scoreboard separate. It covers the rate sweep, error injection and FIFO levels.
What Interviewers Listen For (Senior)
A good senior answer proves the checker with a bank of faulty receivers and a legal variation. It names the escapes and gives an exit criterion.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItScale It
- Verification Plan for a UART
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WhyWhen a Monitor Reports a ByteL1 JuniorL2 Mid-Level
When should a UART monitor publish a byte to the scoreboard, and why not earlier?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
After the stop sample. Until then there is no frame. The stop bit decides between a byte, a framing error and a break, and a break never gives a byte. A monitor that publishes at data bit 7 hands the scoreboard bytes that later turn out to be breaks or errors.
What the Receiver Does After the Stop SampleArrows are decisions in time order, read from the bench receiver. A break is the line held low for longer than a frame. Illustrative sequence- A good stop
The stop sample reads 1: the byte goes to the holding register and the receiver looks for the next start.
- A bad stop
The stop sample reads 0. The byte is delivered with FE, and the receiver waits for the line to go high before it looks for a start.
- Frame or break?
A frame of all zeros with a 0 stop is held back. If the line rises soon, it was a frame: 00 with FE. If it stays low for 176 ticks, it is a break, reported once.
Read the diagram as text
- Stop sample: the last bit of the frame
- Reads 1: deliver the byte
- Reads 0, data not all 0: deliver it with FE
- Reads 0, data all 0: hold it back: frame or break?
- Wait for a high: never start on a low line
- High within 176 ticks: deliver 00 with FE
- 176 low ticks: break_seen; drop the held frame
- Look for a start: eight low ticks again
- Stop sample → Reads 1
- Stop sample → Reads 0, data not all 0
- Stop sample → Reads 0, data all 0
- Reads 1 → Look for a start
- Reads 0, data not all 0 → Wait for a high
- Reads 0, data all 0 → High within 176 ticks
- Reads 0, data all 0 → 176 low ticks
- Wait for a high → Look for a start
The stop sample decides between a byte, a framing error and a break. So the monitor reports only after it.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer publishes the byte after the stop sample.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains the break case, where no byte exists. It keeps verdicts out of the monitor.
- A good stop
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Prove ItProving Your Checker WorksL2 Mid-LevelL3 Senior
Walk me through how you showed that your UART checker would catch a bug, beyond a green regression.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Run it against a bank of deliberately faulty receivers. Examples are a missing overrun flag, an off-centre sample, a one-tick start check and a broken break recovery. Add a legal variation, such as a rate error inside the budget. Every fault must make some check fire, and the legal case must stay silent. A fault that no test catches names the next test to write.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer puts deliberate faults into the design to test the checker.
What Interviewers Listen For (Senior)
A good senior answer builds a matrix of faults against test programs, and adds stimulus until every fault is caught. It insists on a legal variation to catch false alarms.
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Prove ItSolve P6.7.2: Find Five Faulty UART ReceiversSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Break ItUART Bugs That EscapeL3 Senior
Which UART bugs typically survive a decent regression, and what would have caught each?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Rate tolerance worse than claimed: only a sweep to the first failing step catches it. A missing overrun flag: caught only when software reads slowly. The first frame lost after a break: caught by sending a frame right after recovery. An RTS trigger off by one: caught by filling the FIFO to exactly the trigger. Each needs a deliberate scenario; random traffic at the nominal rate rarely hits them.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer names concrete escaped bugs, each with the targeted test that finds it. It does not just ask for more random seeds.
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Scale ItSigning off a UART Link BudgetL2 Mid-LevelL3 Senior
Your SoC talks to a module clocked by an RC oscillator. How do you sign off that the UART link works across temperature and parts?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Add up the error sources: this end's divisor rounding and clock tolerance, and the peer's oscillator tolerance over temperature and voltage. Compare the sum, in both directions, with the receiver's measured budget for the frame format in use, not a quoted 5 %. In simulation, sweep the peer rate in fine steps, both ways, in every supported format. Run frames back to back and with gaps. Record the first failing step as the sign-off number.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer adds up the errors of both ends. It compares them with the budget for the frame format really in use.
What Interviewers Listen For (Senior)
A good senior answer demands a measured first failing step, for each format and direction, as the sign-off number. It leaves margin for a receiver that samples early or late.
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WhyWhy the Baud Budget Is LopsidedL2 Mid-LevelL3 Senior
Why is the measured 8N1 budget +4.5 % on one side and −6 % on the other, not ±5 %?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A rate error moves each sample further from its bit centre, and the stop bit moves most. The total room is about half a bit over the frame. A receiver that samples a little before the centre has less room on one side and more on the other. So quote the budget with its receiver, format and pacing.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Every UART tolerates ±5 %."
The budget depends on the frame format and where the receiver samples. The lesson receiver measured +4.5 % and −6 % for 8N1.
Source ASIC Point lesson P6.4 (measured)
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Prove ItSolve P6.7.1: A UART Monitor That Earns Its VerdictSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Missed Corner
"Loop TX back into RX at the same divisor; if bytes match, the UART works."
Both ends then share one clock, so rate tolerance is never tested. A bug present in both directions, such as reversed bit order, cancels out. Assertions on the receiver's own clock cannot see the peer's bit period either. That needs a rate sweep.
Source ASIC Point lessons P6.7 and P6.4 (the peer's bit period needs a rate sweep)
Half-Truth
"100 % code coverage on the receiver means the plan is done."
Every line of a receiver runs at zero rate error. Shipped bugs hide at the edge of the rate sweep, under slow software reads, or right after a break. Only functional coverage of those conditions shows them.
Wrong Altitude
"I would use a UART VIP and check its scoreboard."
Naming a tool is not a plan. The interviewer wants to hear what is checked, against what model, and what is covered. They also want to know how you show the checker itself catches faults.
Learn It, Then Prove It
- Lesson P6.7Capstone: The UART Monitor, Checker and Bug Hunt
- Lesson P6.4Baud Mismatch: The Measured Budget
- Lesson P6.5Errors, Break and Recovery
- Lesson P6.6Flow Control, FIFOs and Baud Divisors
- Problem P6.7.1A UART Monitor That Earns Its Verdict
- Problem P6.7.2Find Five Faulty UART Receivers
- Problem P6.7.3Find the Lost Frame After Recovery