When a Wire Becomes a Transmission Line

Derive when a trace stops being a plain wire, watch reflections ring on an unterminated line, fix them with series or parallel termination, and see why fast links go differential.

Lesson: P5.10
Time: 30 min
Runs on: Your browser
Check: 4 questions

An SPI flash read cleanly at 25 MHz and failed at 80 MHz, but only on the second board revision. Its clock trace had grown by a few centimetres, and the driver's edges were fast. Each clock edge rang at the flash pin, and one ring crossed the input threshold twice: one edge, two clocks.

TransientThe Same Edge into Three LinesA 1 ns edge behind a 15 Ω driver into ideal 50 Ω lines; the far end of each is a 2 pF receiver.

source edge
far end, TD = t_r/10
far end, TD = t_r/4
far end, TD = 2 t_r

Time 2.3 nssource edge = 3.3 V · far end, TD = t_r/10 = 3.542 V · far end, TD = t_r/4 = 4.069 V · far end, TD = 2 t_r = 0 V
The short line (TD = t_r/10) follows the edge with a small bump: 8.9 % overshoot.
Time 3.4 nssource edge = 3.3 V · far end, TD = t_r/10 = 3.272 V · far end, TD = t_r/4 = 3.292 V · far end, TD = 2 t_r = 1.533 V
At TD = t_r/4 the reflection comes back after half the edge: 23.7 %.
Time 7.2 nssource edge = 3.3 V · far end, TD = t_r/10 = 3.3 V · far end, TD = t_r/4 = 3.292 V · far end, TD = 2 t_r = 5.088 V
The long line (TD = 2 t_r) sees the whole step doubled at its open end, then rings: 55.3 %.

Read the plot as a table

Time	source edge	far end, TD = t_r/10	far end, TD = t_r/4	far end, TD = 2 t_r
0 s	0 V	0 V	0 V	0 V
2.3 ns	3.3 V	3.542 V	4.069 V	0 V
3.4 ns	3.3 V	3.272 V	3.292 V	1.533 V
5 ns	3.3 V	3.3 V	3.351 V	5.077 V
7.2 ns	3.3 V	3.3 V	3.292 V	5.088 V
10 ns	3.3 V	3.3 V	3.299 V	2.343 V
15 ns	3.3 V	3.3 V	3.3 V	3.816 V
20 ns	3.3 V	3.3 V	3.3 V	3.079 V
25 ns	3.3 V	3.3 V	3.3 V	3.244 V
30 ns	3.3 V	3.3 V	3.3 V	3.343 V

Simulated on the Analog engine (ngspice 42), ngspice T elements: ideal lines given by their impedance and one-way delay TD. The edge is a 1 ns ramp, t_r.

The Round Trip Against the Edge

The edge leaves
The driver launches a wave. It reaches the far end after the line's one-way delay, TD.
It comes back
A receiver is almost an open end, so the wave reflects and is back at the driver after 2·TD.
Compare with the edge
If 2·TD is much shorter than the edge time t_r, the reflections arrive while the edge is still rising and blur into it. If 2·TD reaches t_r, the far end sees the whole step reflected before anything corrects it.

TD	One-way delay	Far-end overshoot	Settles within 5 % after
t_r/20	0.05 ns	4.7 %	1.0 ns
t_r/10	0.1 ns	8.9 %	1.3 ns
t_r/6	0.16667 ns	10.0 %	1.5 ns
t_r/4	0.25 ns	23.7 %	2.8 ns
t_r/2	0.5 ns	52.2 %	5.6 ns
t_r	1 ns	55.3 %	10.1 ns
2 t_r	2 ns	55.3 %	19.1 ns

Measured: seven lines in one netlist (data/P5-spice-p510-length.mjs). Settling counts from the start of the edge.

Up to TD = t_r/6 the far end overshoots about 10.0 % or less; by t_r/4 it is 23.7 %, at t_r/2 52.2 %, and from t_r on 55.3 %. So the rule of thumb: keep TD under t_r/6, or treat the trace as a line and terminate it.

To turn that into a length, divide by your board's delay per unit length, t_pd: the longest plain wire is about t_r / (6 · t_pd). Edges set it, not the clock rate: a slow clock with a fast driver still rings.

Reflections, One Arrival at a Time

A Bounce Diagram as a ProgramEach end reflects a fraction Γ = (R − Z0) / (R + Z0) of what arrives. Here Γ is -0.54 at the 15 Ω driver and +1 at the open far end.

Launch
The line looks like 50 Ω to the driver, so it takes 50/65 of the step: a divider.
Open end
All of it reflects, so the far end sees twice the launched wave.
Back at the driver
A driver below 50 Ω, 15 Ω here, reflects it with the sign flipped. The far end now rings around 3.3 V.

Read the diagram as text

Driver: 3.3 V step behind 15 Ω
Outgoing wave: 50 Ω line, 2 ns
Far end: open: Γ = +1
Returning wave: 2 ns back

Driver → Outgoing wave: launch 50/65 of 3.3 V
Outgoing wave → Far end: arrive
Far end → Returning wave: reflect ×1
Returning wave → Driver: reflect ×-0.54

line_model.sv in the example runs exactly this loop for an ideal step and prints every far-end arrival.

Far-end arrival	Far-end voltage
2.0 ns	5.08 V
6.0 ns	2.34 V
10.0 ns	3.82 V
14.0 ns	3.02 V
18.0 ns	3.45 V

Measured: the example, far end open (p510.example). peak 5.08 V, settles within 5 % of 3.30 V at 18.0 ns.

Each round trip multiplies the error by the product of the two Γ, so a driver close to 50 Ω or a far end close to 50 Ω ends the ringing at once. Those are the two terminations.

Series and Parallel Termination

TransientOne Long Line, Three Ways to End ItThe TD = 2 ns line from the figure above: unterminated, a 35 Ω series resistor at the driver, a 50 Ω parallel resistor at the far end.

far end, no termination
line input, series
far end, series
far end, parallel

Time 3 nsfar end, no termination = 9.908 mV · line input, series = 1.65 V · far end, series = 6.44 mV · far end, parallel = 8.952 mV
Series: the line input sits at 1.65 V, half the swing, while the wave travels.
Time 4.2 nsfar end, no termination = 5.008 V · line input, series = 1.65 V · far end, series = 3.255 V · far end, parallel = 2.536 V
The far ends receive their wave. Series doubles to the full swing at the open end; parallel absorbs it.
Time 7.2 nsfar end, no termination = 5.091 V · line input, series = 3.3 V · far end, series = 3.3 V · far end, parallel = 2.6 V
The unterminated end overshoots 55.3 % and keeps ringing until 19.1 ns after the edge starts.

Read the plot as a table

Time	far end, no termination	line input, series	far end, series	far end, parallel
0 s	0 V	0 V	0 V	0 V
3 ns	9.908 mV	1.65 V	6.44 mV	8.952 mV
4.2 ns	5.008 V	1.65 V	3.255 V	2.536 V
5 ns	5.077 V	1.646 V	3.3 V	2.538 V
7.2 ns	5.091 V	3.3 V	3.3 V	2.6 V
10 ns	2.343 V	3.3 V	3.3 V	2.538 V
15 ns	3.815 V	3.3 V	3.3 V	2.539 V
20 ns	3.079 V	3.3 V	3.3 V	2.538 V
25 ns	3.244 V	3.3 V	3.3 V	2.538 V
30 ns	3.343 V	3.3 V	3.3 V	2.538 V

Simulated on the Analog engine (ngspice 42). Same driver, edge and 2 pF receiver as above.

End	Far-end peak	Settles within 5 % after	Cost
None	5.12 V (55.3 %)	19.1 ns	ringing and false edges
Series 35 Ω at the driver	3.30 V	3.1 ns	the line input sits at 1.65 V for 2·TD
Parallel 50 Ω at the far end	2.61 V (2.7 % over its final level)	3.0 ns	a high level of only 2.54 V and 50.8 mA while high

Measured (data/P5-spice-p510-term.mjs). The step model agrees: far end 3.30 V at 2.0 ns with series, far end 2.54 V at 2.0 ns with parallel.

Series termination makes the driver look like 50 Ω: half the swing goes out, doubles at the open far end, and the return is absorbed. It costs no power, but a receiver halfway along sees a half-height step, so it suits one receiver at the end.

Parallel termination absorbs the wave where it lands. Every receiver sees one clean step, but the resistor draws current whenever the line is high. Buses with many receivers, and links that terminate to a mid-level supply, take that cost.

Why Fast Links Go Differential

One Signal on Two WiresThe driver sends +v on one wire and −v on the other; the receiver looks only at the difference.

Two wires, opposite
Each wire carries the other's return current, so the signal does not depend on a clean ground path.
Noise lands on both
A nearby edge or a ground shift adds the same amount to each wire.
Subtract
The receiver takes P − N: the signal doubles and the common noise cancels. A small swing is then enough, and small swings switch fast.

Read the diagram as text

Driver: drives P up and N down together
Wire P: +v
Wire N: −v
Noise: couples into both wires alike
Receiver: reads P − N, terminated across the pair

Driver → Wire P
Driver → Wire N
Wire P → Receiver: +v + noise
Wire N → Receiver: −v + noise
Noise → Wire P
Noise → Wire N

Every idea on this page applies to the pair: it is a transmission line, and it is terminated.

Multi-gigabit links go further down this road: differential pairs terminated at both ends, edges far shorter than any board trace, and a clock recovered from the data (P5.2). The site's high-speed module, coming later, starts from this page.

Where It Shows Up

Lesson	What you meet there
P7.3 SPI timing	the half-cycle budget: a long trace's delay comes out of the time the read data has to return
P7.14 Power-up, pin timing and DC levels	the flash's pin timing at its top clock, measured by a timing checker
P8.1 Who pulls SDA low?	an I2C rise is an RC charge of hundreds of nanoseconds: far slower than any board round trip, so the bus is lumped
P8.13 Heavy buses	series resistors at I2C pins: protection against high-voltage spikes, not termination (UM10204 §7.3)
P9.3 Open-drain and push-pull phases	I3C switches to push-pull for speed, and its edges get sharp
P6.1 Serial links in one picture	a UART byte at console rates lasts tens of microseconds; its edges matter far more than its length

Whether a trace is a line depends on the edge, so the same board can hold lumped I2C wires and SPI lines that need care.

Asked in interviews: signal integrity basics

When must you treat a trace as a transmission line?
When its round trip is not much shorter than the edge. A rule of thumb: one-way delay above about a sixth of the rise time.
Series or parallel termination?
Series for one receiver at the end of a point-to-point line, at no DC cost. Parallel when several receivers sit along the line, at the cost of current.
Why do differential pairs tolerate noise?
Noise couples into both wires alike and the receiver subtracts them, so it cancels.

Try It

Three runs of one ideal step. With the far end open, each line is one arrival: the first is twice the launched wave, and each round trip flips and shrinks the error until it stays within 5 %. With a series resistor or a parallel one, the first arrival is final.

Try ln.rs = 20; (an under-terminated driver), ln.rload = 100; (a far resistor twice too big) or ln.td = 0.1;. The model has no edge time: it is the worst case, and the SPICE figures add the real 1 ns edge.

RUNIcarus Verilog · in your browser

Edit the code, then run it

Expected: -- far end open far end 5.08 V at 2.0 ns far end 2.34 V at 6.0 ns far end 3.82 V at 10.0 ns far end 3.02 V at 14.0 ns far end 3.45 V at 18.0 ns peak 5.08 V, settles within 5 % of 3.30 V at 18.0 ns -- series 35 ohm at the driver far end 3.30 V at 2.0 ns peak 3.30 V, settles within 5 % of 3.30 V at 2.0 ns -- parallel 50 ohm at the far end far end 2.54 V at 2.0 ns peak 2.54 V, settles within 5 % of 2.54 V at 2.0 ns

Read included file: line_model.sv

`timescale 1ns/1ps
// line_model: an ideal (lossless) line of impedance z0 ohm and one-way delay td ns, driven by a step.
// Driver: a vs volt step behind rd ohm, then a series resistor rs. Parallel resistors to ground at the
// line's input (rnear) and at its far end (rload); 1e12 means none.
// One wave travels the line. At each end it reflects with that end's coefficient
// (R - z0) / (R + z0), and the far end adds up what arrives.
module line_model;
  real vs = 3.3, rd = 15, rs = 0, rnear = 1e12, rload = 1e12, z0 = 50, td = 2;
  real first, peak, final_v, settled;    // first far-end arrival, highest, DC level, settling time (ns)
  bit trace = 1;                         // print each far-end arrival until the end settles
  function automatic real mag(input real x); return x < 0 ? -x : x; endfunction
  task automatic step();
    real rth, vth, gs, gl, rp, wave, far, t0, t; bit done;
    rth = (rd + rs) * rnear / (rd + rs + rnear);     // the driver as the line sees it
    vth = vs * rnear / (rd + rs + rnear);
    gs = (rth - z0) / (rth + z0);                    // reflection at the driver end
    gl = (rload - z0) / (rload + z0);                // reflection at the far end
    rp = rnear * rload / (rnear + rload);
    final_v = vs * rp / (rd + rs + rp);              // at DC the line is a wire
    wave = vth * z0 / (rth + z0);                    // the step the line takes at t = 0
    far = 0; peak = 0; settled = -1; t0 = $realtime; done = 0;
    for (int k = 0; k < 60 && !done; k++) begin
      #(td); t = $realtime - t0;
      far = far + wave * (1 + gl); wave = wave * gl;  // arrival and reflection at the far end
      if (k == 0) first = far;
      if (far > peak) peak = far;
      if (mag(far - final_v) > 0.05 * final_v) settled = -1; else if (settled < 0) settled = t;
      if (trace && (k == 0 || settled < 0 || settled == t)) $display("far end %.2f V at %0.1f ns", far, t);
      #(td); wave = wave * gs;                       // back at the driver: reflect again
      done = mag(wave) < 1e-6;                       // nothing left travelling
    end
    if (trace) $display("peak %.2f V, settles within 5 %% of %.2f V at %0.1f ns", peak, final_v, settled);
  endtask
endmodule

Check Yourself

Predict the outputBench defaults: a 3.3 V step behind a 15 Ω driver into a 50 Ω line, 2 ns one way, far end open. The program prints the far end's first arrival. What does it print?

`timescale 1ns/1ps
module tb;
  line_model ln();    // defaults: 3.3 V step, 15 ohm driver, 50 ohm line, 2 ns one way, far end open
  initial begin
    ln.trace = 0;
    ln.step();
    $display("first arrival %.2f V", ln.first);
    $finish;
  end
endmodule

Read included file: line_model.sv

`timescale 1ns/1ps
// line_model: an ideal (lossless) line of impedance z0 ohm and one-way delay td ns, driven by a step.
// Driver: a vs volt step behind rd ohm, then a series resistor rs. Parallel resistors to ground at the
// line's input (rnear) and at its far end (rload); 1e12 means none.
// One wave travels the line. At each end it reflects with that end's coefficient
// (R - z0) / (R + z0), and the far end adds up what arrives.
module line_model;
  real vs = 3.3, rd = 15, rs = 0, rnear = 1e12, rload = 1e12, z0 = 50, td = 2;
  real first, peak, final_v, settled;    // first far-end arrival, highest, DC level, settling time (ns)
  bit trace = 1;                         // print each far-end arrival until the end settles
  function automatic real mag(input real x); return x < 0 ? -x : x; endfunction
  task automatic step();
    real rth, vth, gs, gl, rp, wave, far, t0, t; bit done;
    rth = (rd + rs) * rnear / (rd + rs + rnear);     // the driver as the line sees it
    vth = vs * rnear / (rd + rs + rnear);
    gs = (rth - z0) / (rth + z0);                    // reflection at the driver end
    gl = (rload - z0) / (rload + z0);                // reflection at the far end
    rp = rnear * rload / (rnear + rload);
    final_v = vs * rp / (rd + rs + rp);              // at DC the line is a wire
    wave = vth * z0 / (rth + z0);                    // the step the line takes at t = 0
    far = 0; peak = 0; settled = -1; t0 = $realtime; done = 0;
    for (int k = 0; k < 60 && !done; k++) begin
      #(td); t = $realtime - t0;
      far = far + wave * (1 + gl); wave = wave * gl;  // arrival and reflection at the far end
      if (k == 0) first = far;
      if (far > peak) peak = far;
      if (mag(far - final_v) > 0.05 * final_v) settled = -1; else if (settled < 0) settled = t;
      if (trace && (k == 0 || settled < 0 || settled == t)) $display("far end %.2f V at %0.1f ns", far, t);
      #(td); wave = wave * gs;                       // back at the driver: reflect again
      done = mag(wave) < 1e-6;                       // nothing left travelling
    end
    if (trace) $display("peak %.2f V, settles within 5 %% of %.2f V at %0.1f ns", peak, final_v, settled);
  endtask
endmodule

Spot the bugEach option sets the resistors of the lesson's line model (3.3 V step, 15 Ω driver, 50 Ω line, 2 ns one way, far end open) before one step. The bench fails if the far end peaks more than 10 % above its final level or settles later than three one-way delays. Which termination fails?

ln.rnear = 50;

ln.rs = 35;

ln.rload = 50;

ln.rs = 33;

Read included file: line_model.sv

`timescale 1ns/1ps
// line_model: an ideal (lossless) line of impedance z0 ohm and one-way delay td ns, driven by a step.
// Driver: a vs volt step behind rd ohm, then a series resistor rs. Parallel resistors to ground at the
// line's input (rnear) and at its far end (rload); 1e12 means none.
// One wave travels the line. At each end it reflects with that end's coefficient
// (R - z0) / (R + z0), and the far end adds up what arrives.
module line_model;
  real vs = 3.3, rd = 15, rs = 0, rnear = 1e12, rload = 1e12, z0 = 50, td = 2;
  real first, peak, final_v, settled;    // first far-end arrival, highest, DC level, settling time (ns)
  bit trace = 1;                         // print each far-end arrival until the end settles
  function automatic real mag(input real x); return x < 0 ? -x : x; endfunction
  task automatic step();
    real rth, vth, gs, gl, rp, wave, far, t0, t; bit done;
    rth = (rd + rs) * rnear / (rd + rs + rnear);     // the driver as the line sees it
    vth = vs * rnear / (rd + rs + rnear);
    gs = (rth - z0) / (rth + z0);                    // reflection at the driver end
    gl = (rload - z0) / (rload + z0);                // reflection at the far end
    rp = rnear * rload / (rnear + rload);
    final_v = vs * rp / (rd + rs + rp);              // at DC the line is a wire
    wave = vth * z0 / (rth + z0);                    // the step the line takes at t = 0
    far = 0; peak = 0; settled = -1; t0 = $realtime; done = 0;
    for (int k = 0; k < 60 && !done; k++) begin
      #(td); t = $realtime - t0;
      far = far + wave * (1 + gl); wave = wave * gl;  // arrival and reflection at the far end
      if (k == 0) first = far;
      if (far > peak) peak = far;
      if (mag(far - final_v) > 0.05 * final_v) settled = -1; else if (settled < 0) settled = t;
      if (trace && (k == 0 || settled < 0 || settled == t)) $display("far end %.2f V at %0.1f ns", far, t);
      #(td); wave = wave * gs;                       // back at the driver: reflect again
      done = mag(wave) < 1e-6;                       // nothing left travelling
    end
    if (trace) $display("peak %.2f V, settles within 5 %% of %.2f V at %0.1f ns", peak, final_v, settled);
  endtask
endmodule

ConceptFrom the measured sweep (1 ns edge, 15 Ω driver, 2 pF receiver), which statement is right?

The clock rate decides it: at a low clock rate any line behaves as a plain wireA line whose one-way delay is half the edge already overshoots almost as much as a very long lineOvershoot grows in proportion to the line's length, so a line twice as long rings twice as hardA line shorter than the edge never overshoots, because the reflection is back before the edge ends

ConceptA clock line is series terminated at its driver. A designer adds a second receiver halfway along it. What goes wrong?

The driver must now source twice the current, so its output level drops below the thresholdNothing: series termination makes every point on the line settle to the full swing at onceThe middle sits near half the swing until the far-end reflection passes it, so its edge has a stepThe far receiver now overshoots, because the second receiver reflects the wave back at it

Remember

A trace is a transmission line when its round trip is not much shorter than the edge: keep the one-way delay under about t_r/6.
Each end reflects (R − Z0) / (R + Z0) of what arrives; an open end doubles the wave, a low-impedance driver flips it back.
Series termination matches the driver: no DC cost, but only a receiver at the far end sees a clean edge.
Parallel termination matches the far end: every receiver sees one step, at the cost of current while high.
Fast links go differential: the receiver subtracts two opposite wires, so common noise cancels and small swings suffice.

Find Your Next Track

Put Your Skills to Work

Prepare to Explain Your Thinking

An Idea to Try? Pick a Tool.

When a Wire Becomes a Transmission Line

The Round Trip Against the Edge

Reflections, One Arrival at a Time

Series and Parallel Termination

Why Fast Links Go Differential

Where It Shows Up

Try It

Check Yourself

Remember