Line Drivers: Push-Pull and Open-Drain

Two Ways to Drive a Wire

Push-pull buys speed and pays in sharing: two push-pull outputs on one wire must never both be on. Open drain buys sharing and pays in speed: the rise is only as fast as the resistor can charge the wire.

Who Pulls Low: The Wired-AND

The line reads 1 only when every device lets go, which is an AND of the devices' released states. A device can always pull, never fight, and read the line back to see whether someone else pulls too. I2C builds clock stretching and arbitration on this (P8.5, P8.6).

Two Push-Pull Outputs on One Wire

The same program puts two push-pull outputs on one wire. Driving the same value is harmless: 1. Driving opposite values gives x, the simulator's word for the fight in the opening plot.

A bench for a shared line should run on a four-state simulator, or check for contention itself. Otherwise a missing pull-up and two drivers fighting both pass.

The Price of Open Drain: The Rise

Every released rise is the same curve scaled by R × C. The 1 kΩ, 100 pF run measures 0.847 × RC, the constant UM10204 §7.1 derives from the 0.3 and 0.7 VDD thresholds. A smaller resistor is faster but makes every pull-down sink more current. Lesson P8.7 sizes it.

Where You Will Meet It

Try It

The sda net is declared tri1: a pull-up the simulator models. The bare net is a plain wire with the same two open-drain outputs and nothing pulling it up. fight has two push-pull outputs.

Change tri1 sda; to wire sda;: the released rows of sda read z too. Then try tri0 sda;, a pull-down, and see which rows change.

`timescale 1ns/1ns
module od(input wire low, inout wire line); assign line = low ? 1'b0 : 1'bz; endmodule
module pp(input wire en, input wire v, inout wire line); assign line = en ? v : 1'bz; endmodule

Check Yourself

`timescale 1ns/1ns
module tb;
  tri1 sda;                         // the pull-up
  reg ctrl_low = 0, tgt_en = 0;
  od ctrl(ctrl_low, sda);           // the controller: open drain
  pp tgt(tgt_en, 1'b1, sda);        // a target whose output is push-pull, driving 1
  reg first;
  initial begin
    tgt_en = 1;      #1 first = sda;   // the target drives 1; nobody pulls
    ctrl_low = 1;    #1 $display("%b %b", first, sda);
    $finish;
  end
endmodule

`timescale 1ns/1ns
module od(input wire low, inout wire line); assign line = low ? 1'b0 : 1'bz; endmodule
module pp(input wire en, input wire v, inout wire line); assign line = en ? v : 1'bz; endmodule

assign line = low ? 1'b0 : 1'bz;

assign line = !low ? 1'bz : 1'b0;

assign line = low ? 1'b0 : 1'b1;

bufif1 (line, 1'b0, low);