Crossing into the Receiver's Clock

A Sample Inside the Window

A flop needs its input steady for a short window around the clock edge. A serial input owes nothing to the receiver's clock, so sooner or later it changes inside that window. The flop then sits between 0 and 1 and settles late, to either value.

One Flop or Two

The example sends 20000 edges at seeded random times into a 10 ns clock. Each design has two readers. A read is late when the input was still settling; a split is a clock in which the two readers disagree.

meta_flop sync1 (clk, rx, s1);
meta_flop read_a1 (clk, s1, a1);
meta_flop read_b1 (clk, s1, b1);

meta_flop sync1 (clk, rx, s1);
meta_flop sync2 (clk, s1, s2);
meta_flop read_a2 (clk, s2, a2);

A second flop does not prevent metastability. It buys the first flop one whole clock to settle, and long settles get exponentially rarer. The standard form of the failure rate writes this as MTBF = e^(t_r / τ) / (T_0 · f_clk · f_data), where t_r is the settling time the design allows and τ and T_0 belong to the flop.

Each extra flop adds about one clock period to t_r. Use the formula to compare designs; the numbers for a real flop come from its library, never from this model.

Spikes and the Glitch Filter

A synchronizer makes a clean 0 or 1 out of every sample, including a sample of a noise spike. A filter decides how many samples must agree before the output changes. The bench samples every 10 ns and sends 200 seeded low spikes per width.

A spike shorter than one sample period covers at most one sample, so a 2-of-3 vote never passes one: 0 of 200 at 8 ns. In general, N in a row rejects every spike shorter than N − 1 periods and delays every real edge by N − 1 clocks.

An I2C Fast-mode input must suppress spikes shorter than 50 ns (UM10204 §5.1; §6.1, Table 10, tSP and note 8). At a 10 ns sample clock that is six in a row: 0 of 200 spikes pass at 45 ns, 93 at 55 ns.

Where It Shows Up

Try It

The first line counts the edges and how many landed inside the first flop's 1 ns window. The next two lines are the twin: the readers of s1 sampled a settling input 26 times and split 16 times; the readers of s2 never did.

Change the clock to always #3 clk = ~clk; and pass .T(6.0) to every flop: the two-flop line stops reading 0. Then try .TAU(1.0) on sync1 and sync2, a faster flop.

`timescale 1ns/1ps
// meta_flop: a D flip-flop with a metastability window. A teaching model, not a cell library.
//  - d changed less than W ns before the clock edge, or d is still unresolved (x): q goes to x and
//    resolves to a seeded random 0 or 1 after a seeded random time t, with P(t > x) = exp(-x / TAU).
//  - otherwise q copies d, TCO ns after the edge.
// T is the clock period: the next edge samples again, so a resolution is cut off there.
// TRES > 0 fixes the resolution time (used for the one-event figure).
module meta_flop #(parameter real T = 10.0, W = 1.0, TCO = 0.1, TAU = 2.0, TRES = 0.0,
                   parameter int SEED = 1)
                  (input wire clk, d, output reg q = 0);
  realtime changed = -1.0e9;          // when d last changed
  reg [31:0] seed = SEED;
  int samples = 0, meta = 0;          // edges seen, and edges that sampled inside the window
  real t; reg v;
  function automatic real uniform();  // (0, 1]
    seed = seed * 32'd1664525 + 32'd1013904223;
    return ((seed >> 8) + 1.0) / 16777216.0;
  endfunction
  always @(d) changed = $realtime;
  always @(posedge clk) begin
    samples++;
    if (d === 1'bx || $realtime - changed < W) begin
      meta++;
      v = uniform() < 0.5;
      t = TRES > 0 ? TRES : -TAU * $ln(uniform());
      if (t > T - 0.002) t = T - 0.002;
      q <= #(TCO) 1'bx;
      q <= #(TCO + t) v;
    end else q <= #(TCO) d;
  end
endmodule

Check Yourself

`timescale 1ns/1ps
module tb;
  reg clk = 0, rx = 1;                          // the line idles high
  always #5 clk = ~clk;                         // the receiver samples every 10 ns
  wire none, vote3, vote5, run6;
  vote_filter #(.M(1), .N(1)) f_none  (clk, rx, none);
  vote_filter #(.M(3), .N(2)) f_vote3 (clk, rx, vote3);
  vote_filter #(.M(5), .N(3)) f_vote5 (clk, rx, vote5);
  vote_filter #(.M(6), .N(6)) f_run6  (clk, rx, run6);
  // A spike passes when it pulls a filter's output low.
  int p_none = 0, p_vote3 = 0, p_vote5 = 0, p_run6 = 0;
  always @(negedge none) p_none++;
  always @(negedge vote3) p_vote3++;
  always @(negedge vote5) p_vote5++;
  always @(negedge run6) p_run6++;
  reg [31:0] seed = 32'd20261108;
  // n low spikes of the given width, at seeded random times 300 to 500 ns apart.
  task automatic spikes(input real width, input int n);
    repeat (n) begin
      seed = seed * 32'd1664525 + 32'd1013904223;
      #(300.0 + (seed >> 8) / 16777216.0 * 200.0);
      rx = 0; #(width); rx = 1;
    end
    #200;
  endtask
  task automatic clear(); p_none = 0; p_vote3 = 0; p_vote5 = 0; p_run6 = 0; endtask
  initial begin
    spikes(8, 200);                             // 200 spikes, each 8 ns wide
    $display("2-of-3 passed %0d of 200", p_vote3);
    $finish;
  end
endmodule

`timescale 1ns/1ps
// vote_filter: samples d on every clock edge and keeps the last M samples. The output goes to 1 when at
// least N of them are 1 and to 0 when at least N are 0; otherwise it holds.
//   M = 1, N = 1: no filter.  M = 3, N = 2: a 2-of-3 vote.  M = 5, N = 3: 3-of-5.  M = N: N in a row.
module vote_filter #(parameter int M = 3, N = 2) (input wire clk, d, output reg q = 1);
  reg [7:0] last = 8'hff; int ones;
  always @(posedge clk) begin
    last = {last[6:0], d};
    ones = 0;
    for (int i = 0; i < M; i++) ones += last[i];
    if (ones >= N) q <= 1; else if (M - ones >= N) q <= 0;
  end
endmodule

wire s1, s2;
meta_flop #(.SEED(11)) f1 (clk, rx, s1);
meta_flop #(.SEED(22)) f2 (clk, s1, s2);
assign rx_s = s2;

wire s1;
meta_flop #(.SEED(11)) f1 (clk, rx, s1);
assign rx_s = s1;

wire s1, s2, s3;
meta_flop #(.SEED(11)) f1 (clk, rx, s1);
meta_flop #(.SEED(22)) f2 (clk, s1, s2);
meta_flop #(.SEED(77)) f3 (clk, s2, s3);
assign rx_s = s3;

wire s1, s2, s3, s4;
meta_flop #(.SEED(11)) f1 (clk, rx, s1);
meta_flop #(.SEED(22)) f2 (clk, s1, s2);
meta_flop #(.SEED(77)) f3 (clk, s2, s3);
meta_flop #(.SEED(88)) f4 (clk, s3, s4);
assign rx_s = (s2 & s3) | (s3 & s4) | (s2 & s4);

`timescale 1ns/1ps
// meta_flop: a D flip-flop with a metastability window. A teaching model, not a cell library.
//  - d changed less than W ns before the clock edge, or d is still unresolved (x): q goes to x and
//    resolves to a seeded random 0 or 1 after a seeded random time t, with P(t > x) = exp(-x / TAU).
//  - otherwise q copies d, TCO ns after the edge.
// T is the clock period: the next edge samples again, so a resolution is cut off there.
// TRES > 0 fixes the resolution time (used for the one-event figure).
module meta_flop #(parameter real T = 10.0, W = 1.0, TCO = 0.1, TAU = 2.0, TRES = 0.0,
                   parameter int SEED = 1)
                  (input wire clk, d, output reg q = 0);
  realtime changed = -1.0e9;          // when d last changed
  reg [31:0] seed = SEED;
  int samples = 0, meta = 0;          // edges seen, and edges that sampled inside the window
  real t; reg v;
  function automatic real uniform();  // (0, 1]
    seed = seed * 32'd1664525 + 32'd1013904223;
    return ((seed >> 8) + 1.0) / 16777216.0;
  endfunction
  always @(d) changed = $realtime;
  always @(posedge clk) begin
    samples++;
    if (d === 1'bx || $realtime - changed < W) begin
      meta++;
      v = uniform() < 0.5;
      t = TRES > 0 ? TRES : -TAU * $ln(uniform());
      if (t > T - 0.002) t = T - 0.002;
      q <= #(TCO) 1'bx;
      q <= #(TCO + t) v;
    end else q <= #(TCO) d;
  end
endmodule