Interview Question · Concept
Pipeline Hazards and Forwarding
- Asked at Apple
- Asked at NVIDIA
The Question
The interviewer asks
What hazards does a five-stage in-order pipeline have, and how does forwarding help?
You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A data hazard (read after write) happens when an instruction needs a result that is still in the pipeline. A structural hazard is two instructions needing one resource, and a control hazard is a branch that changes which instructions follow. Forwarding sends a result from a later stage straight to the next instruction's EX input. That removes most data stalls, but a load followed by a use still costs one bubble.
- A RAW hazard
The next instruction reads a register in ID before the producer has written it in WB.
- Forward from EX/MEM
An ALU result exists at the end of EX. The forward mux hands it to the very next instruction.
- Forward from MEM/WB
Two instructions later, the result sits in MEM/WB. A second path serves that distance.
- Load-use
A load has its data only at the end of MEM, one stage too late for the next EX. That case still stalls one cycle.
Read the diagram as text
- IF: fetch the instruction
- ID: decode, read registers
- EX: the ALU
- MEM: load or store data
- WB: write the register file
- Forward mux: picks the ALU operand
- IF → ID
- ID → EX
- EX → MEM
- MEM → WB
- MEM → Forward mux: EX/MEM result: distance 1
- WB → Forward mux: MEM/WB result: distance 2
- Forward mux → EX: operand
Each forwarding path serves one distance between producer and consumer.
A cycle-count model of the classic five-stage pipeline: a load followed by three dependent instructions.
no forwarding: stall cycles = 6 full forwarding: stall cycles = 1Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer names RAW, structural and control hazards, with a two-instruction example for each. It draws the forwarding path from EX/MEM back to EX.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains why the load-use case still stalls. It mentions that the compiler can schedule instructions to hide that stall.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfCompareScale It
- Pipeline Hazards and Forwarding
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WhyWhy Forwarding Cannot Hide a Load-Use HazardL1 JuniorL2 Mid-Level
Why can forwarding hide an ALU-to-ALU dependency but not a load followed by a use?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
An ALU result exists at the end of EX, just in time for the next instruction's EX. A load's data exists only at the end of MEM, one stage later. Forwarding cannot send data back in time, so the dependent instruction waits one cycle.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Add a forwarding path from MEM to EX and the stall goes away."
That path exists already. The problem is timing: the data arrives at the end of the cycle in which EX needs it.
Source Hennessy and Patterson, Computer Architecture: A Quantitative Approach (5th ed.), App. C, data hazards that need stalls; shown by the run on this question
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CompareRAW, WAR and WAW HazardsL1 JuniorL2 Mid-Level
Compare RAW, WAR and WAW hazards. Which ones can a simple in-order five-stage pipeline have?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
RAW: a read must see an earlier write. WAR: a later write must not land before an earlier read. WAW: two writes must land in program order. In a simple in-order pipeline, reads happen in ID and writes in WB, both in order, so only RAW occurs. WAR and WAW appear with out-of-order issue or units of different latency.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Every pipeline must handle all three."
They depend on when reads and writes happen. In-order reads in ID and in-order writes in WB rule out WAR and WAW.
Source Hennessy and Patterson, Computer Architecture: A Quantitative Approach (5th ed.), App. C, Pipelining: Basic and Intermediate Concepts
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Scale ItWhat a Deeper Pipeline Does to HazardsL2 Mid-LevelL3 Senior
Scale it: the team doubles the pipeline depth to raise the clock. What happens to hazards and performance?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Each stage does less work, so the clock rises. But results take more stages to appear, so dependent instructions wait more cycles. Branches resolve later and flush more instructions, and forwarding paths multiply. Performance grows only if the clock gain beats the extra stall cycles, so measure it on real code.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Twice the stages means twice the performance."
The stall and flush cycles grow with depth. The register overhead per stage also stops the clock from doubling.
Source Lesson R4.2, Latency, throughput and registered outputs
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What IfBranches and the Control HazardL1 JuniorL2 Mid-Level
Asked if they mention branches
What if a taken branch goes through this pipeline? What happens to the instructions behind it?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The pipeline has already fetched the next instructions on the wrong path. When the branch resolves, they must be flushed, and each flushed slot is a lost cycle. Resolving earlier or predicting the branch cuts the penalty. A flushed instruction must never write a register or memory.
Self-Check
Tick each key point you covered in your answer.
Missed Corner
"A flushed instruction simply does nothing."
Only if the flush clears its write enables at every stage. A missed enable lets a wrong-path instruction write a register.
Source Hennessy and Patterson, Computer Architecture: A Quantitative Approach (5th ed.), App. C, Pipelining: Basic and Intermediate Concepts
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"Forwarding removes every stall."
A load's data exists only at the end of MEM, after the next instruction needed it in EX. The twin still counts one stall; filling the slot removes it.
Run It
The same program with full forwarding.
full forwarding: stall cycles = 1 FAIL: forwarding left a stall: a load's data is ready only after MEM, one cycle too lateSee the Fix
module tb;
// A cycle-count model of the classic in-order five-stage pipeline (IF ID EX MEM WB).
// Rules: an ALU result can be forwarded to the next instruction's EX; a load's data exists only
// after MEM, so a dependent EX waits one extra cycle; without forwarding, a value is read in ID
// during the producer's WB (write in the first half, read in the second).
localparam int N = 5;
int dst [N], s1 [N], s2 [N];
bit ld [N];
int ex [N];
task automatic schedule(input bit fwd, output int stalls);
int t, rdy, prev;
stalls = 0;
for (int i = 0; i < N; i++) begin
prev = (i == 0) ? -1 : ex[i-1];
t = prev + 1; // in order, one instruction per cycle
for (int j = 0; j < i; j++)
if (dst[j] != 0 && (dst[j] == s1[i] || dst[j] == s2[i])) begin
rdy = fwd ? ex[j] + (ld[j] ? 2 : 1) : ex[j] + 3;
if (rdy > t) t = rdy;
end
stalls += t - (prev + 1);
ex[i] = t;
end
endtask
int st_off, st_on;
initial begin
dst[0] = 1; s1[0] = 0; s2[0] = 0; ld[0] = 1; // lw r1, 0(r0)
dst[1] = 5; s1[1] = 6; s2[1] = 7; ld[1] = 0; // or r5, r6, r7
dst[2] = 2; s1[2] = 1; s2[2] = 1; ld[2] = 0; // add r2, r1, r1
dst[3] = 3; s1[3] = 2; s2[3] = 1; ld[3] = 0; // sub r3, r2, r1
dst[4] = 4; s1[4] = 3; s2[4] = 0; ld[4] = 0; // and r4, r3, r0
schedule(1, st_on);
$display("full forwarding: stall cycles = %0d", st_on);
if (st_on == 0) $display("PASS: an independent instruction in the load slot hides the bubble");
end
endmodule
Prints: full forwarding: stall cycles = 0 PASS: an independent instruction in the load slot hides the bubble
Buzzword Without Mechanism
Recites "RAW, WAR, WAW" and stops.
In a simple in-order pipeline, only RAW occurs. The interviewer wants the stage where the value is made and the stage that needs it.