Interview Question · Concept
Write-Through vs Write-Back Caches
The Question
The interviewer asks
Compare write-through and write-back caches. What does each mean for memory traffic and for other agents that read memory?
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Reveal the Model Answer
Write-through sends every store to memory, so memory always has the latest data, but traffic is high. Write-back updates only the cache and marks the line dirty, and memory is written when the line is evicted. That saves traffic, but memory can be stale. Any other reader of memory, such as a DMA engine, then needs coherence hardware or software cleaning.
- Write-through
Every store also goes to memory. Memory is always current, but traffic is high.
- Write-back
Stores stay in the line and set the dirty bit. Memory is written once, when the line is evicted.
- Stale memory
Until that eviction, a DMA read of memory gets the old data, unless software cleans the line first.
Read the diagram as text
- CPU: issues stores
- Cache line: data and a dirty bit
- Eviction: dirty line written back
- Memory: main copy
- DMA engine: reads memory directly
- CPU → Cache line: store
- Cache line → Memory: write-through: every store
- Cache line → Eviction: write-back: on eviction
- Eviction → Memory
- Memory → DMA engine: read
Write-back saves memory traffic. The price is that memory can be stale for other readers.
Sixteen stores to one cached line, then an eviction.
write-through: 16 memory writes; write-back: 1 line write at evictionSelf-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer counts the memory writes for a burst of stores under each policy. It then names the risk of stale memory with write-back.
What Interviewers Listen For (Senior)
A good senior answer names who keeps memory coherent: snooping hardware, or software clean and invalidate calls around DMA. It says what a test must do to catch a missing clean.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfCompareScale It
- Write-Through vs Write-Back Caches
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CompareWrite-Allocate vs No-Write-AllocateL2 Mid-Level
Compare write-allocate with no-write-allocate on a store miss.
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Reveal the Model Answer
Write-allocate fetches the line on a store miss and then writes into the cache. It helps when nearby data is used again soon. No-write-allocate sends the store straight to memory and leaves the cache alone. It suits streaming writes that are never read back. Write-back caches usually allocate; write-through caches often do not.
Self-Check
Tick each key point you covered in your answer.
Missed Corner
"A store miss never needs a memory read."
With write-allocate it does: the rest of the line must be fetched before the store can merge into it.
Source Hennessy and Patterson, Computer Architecture: A Quantitative Approach (5th ed.), App. B, Review of Memory Hierarchy
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WhyWhy a Write-Back Cache Needs a Dirty BitL1 JuniorL2 Mid-Level
Why does a write-back cache keep a dirty bit per line?
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Reveal the Model Answer
The dirty bit records that the line differs from memory. On eviction, a clean line can simply be dropped, while a dirty one must be written back first. Without the bit, the cache would write back every evicted line and lose much of its saving.
Self-Check
Tick each key point you covered in your answer.
Misconception
"The valid bit already says whether to write back."
Valid says the line holds real data. Dirty says that data is newer than memory. A clean valid line needs no write-back.
Source Hennessy and Patterson, Computer Architecture: A Quantitative Approach (5th ed.), App. B, Review of Memory Hierarchy
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What IfA DMA Write Behind the CacheL2 Mid-LevelL3 Senior
Asked if they mention DMA
What if the DMA writes memory and then the CPU reads the same address?
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Reveal the Model Answer
If the CPU still caches that line, it hits its own old copy and never sees the DMA data. Without coherence hardware, software must invalidate the line before reading. Before a DMA reads memory, software must clean dirty lines instead.
Self-Check
Tick each key point you covered in your answer.
Missed Corner
"Cleaning the cache before the DMA is enough in both directions."
Cleaning pushes CPU data out to memory. After a DMA write, the CPU also needs its copy invalidated, as the twin shows.
Run It
The line is clean but still cached when the DMA writes 0x77 to memory.
RUNIcarus Verilog · in your browserExpected:CPU reads address 3: 55FAIL: the CPU hit its stale cached copy and never saw the DMA writeSee the Fix
module tb; logic [7:0] mem [16]; // main memory, word addresses 0..15 logic [7:0] line_data; logic [3:0] line_addr; bit line_valid = 0, dirty = 0; task automatic cpu_write(input logic [3:0] a, input logic [7:0] d); line_addr = a; line_data = d; line_valid = 1; dirty = 1; // write-back: memory later endtask function automatic logic [7:0] cpu_read(input logic [3:0] a); return (line_valid && line_addr == a) ? line_data : mem[a]; endfunction task automatic clean_line(); // write a dirty line back to memory if (line_valid && dirty) begin mem[line_addr] = line_data; dirty = 0; end endtask initial begin foreach (mem[i]) mem[i] = 8'h00; cpu_write(4'd3, 8'h55); clean_line(); // the line is now clean but still cached mem[3] = 8'h77; // a DMA writes new data into memory line_valid = 0; // software invalidates the line before reading $display("CPU reads address 3: %h", cpu_read(4'd3)); if (cpu_read(4'd3) == 8'h77) $display("PASS: invalidating the line made the CPU read the DMA data"); end endmodulePrints:
CPU reads address 3: 77PASS: invalidating the line made the CPU read the DMA data -
Scale ItTwo CPUs with Write-Back CachesL3 Senior
Scale it: two CPUs each have a write-back cache over shared memory. What new problem appears, and how is it verified?
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Reveal the Model Answer
Both caches can hold the same line, and one CPU's write leaves the other's copy stale. A coherence protocol such as MESI tracks each line's state and snoops or invalidates the other copy. Verification runs both CPUs at once on the same lines, including different bytes of one line. A memory reference model then checks every read.
Self-Check
Tick each key point you covered in your answer.
Wrong Altitude
Tests each CPU alone and calls coherence covered.
Coherence bugs need both CPUs touching the same line at nearly the same time. Single-CPU tests never create that.
Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 17.2 Identify subsystems within the cache subsystem
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"With write-back, memory always holds the latest data once the store completes."
The store completes in the cache. Memory gets the data only on eviction or a clean, so the twin's DMA reads the old value.
Run It
The CPU stores 0x55 to address 3 in a write-back cache; a DMA reads address 3 from memory.
DMA reads address 3 from memory: 00 FAIL: with write-back, memory still held the old value; the new one was only in the cacheSee the Fix
module tb;
logic [7:0] mem [16]; // main memory, word addresses 0..15
logic [7:0] line_data; logic [3:0] line_addr; bit line_valid = 0, dirty = 0;
task automatic cpu_write(input logic [3:0] a, input logic [7:0] d);
line_addr = a; line_data = d; line_valid = 1;
dirty = 1; // write-back: memory later
endtask
function automatic logic [7:0] cpu_read(input logic [3:0] a);
return (line_valid && line_addr == a) ? line_data : mem[a];
endfunction
task automatic clean_line(); // write a dirty line back to memory
if (line_valid && dirty) begin mem[line_addr] = line_data; dirty = 0; end
endtask
initial begin
foreach (mem[i]) mem[i] = 8'h00;
cpu_write(4'd3, 8'h55); // the CPU updates address 3
clean_line(); // software cleans the line before the DMA
$display("DMA reads address 3 from memory: %h", mem[3]);
if (mem[3] == 8'h55) $display("PASS: cleaning the dirty line first gave the DMA the new data");
end
endmodule
Prints: DMA reads address 3 from memory: 55 PASS: cleaning the dirty line first gave the DMA the new data
Half-Truth
"Write-through needs no coherence."
Memory is current, but other caches or the CPU's own copy can still be stale after a DMA writes memory.
Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 17.1 Cache subsystem (L1 write-through, L2 write-back MESI)