Interview Question · Concept
Latency Versus Throughput in a Pipeline
The Question
The interviewer asks
You add a register stage in the middle of a slow datapath. What happens to latency, throughput and the clock frequency?
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Reveal the Model Answer
Latency in cycles goes up by one, because every result passes one more register. Throughput stays at one result per cycle, but each cycle can now be shorter. So results per second go up if the cut really shortens the slowest stage. The register also costs flops and power. The clock is set by the slowest stage, not the average.
y is the shipped design; y_r is the same design with a register on the output.- Cycle 2
Edge 2 takes a = 1, b = 10, c = 0. The shipped design shows y = 10 after the same edge: latency 1.
- Cycle 3
The registered version shows 10 one edge later. Its latency is 2.
- Cycle 9
Both versions give one result per edge for the whole burst. Throughput is one per cycle either way.
- Cycle 10
The registered version delivers its last result, 87, at edge 10, one edge after the shipped design.
One value per edge, printed by the bench after each edge settles. Registering the output moved every result one edge later and kept the spacing.
| Design | Latency (cycles) | Results per cycle | Levels of logic | Flops |
|---|---|---|---|---|
dot_flat: one stage | 1 | 1 | 37 | 17 |
dot_pipe: products, then sum | 2 | 1 | 31 | 49 |
Measured on the pinned Yosys flow. The cut removed only 6 levels, because one 8-bit multiplier alone is about 31 levels deep.
The one-stage dot product a0b0 + a1b1, checked for a one-cycle latency.
dot_flat: results matching a latency of 1 cycle: 17 of 17Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer says latency goes up by one cycle and throughput stays at one result per cycle. It explains why the clock can now be faster.
What Interviewers Listen For (Junior)
A good junior answer asks where the slowest stage is before it promises a faster clock. It notices that the gain is small here, because the multiplier is the slowest part.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItCompare
- Latency Versus Throughput in a Pipeline
-
WhyThe Slowest Stage Sets the ClockL1 Junior
Why did the cut in the dot product save only 6 levels of logic, not half of them?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The clock must fit the slowest stage. The products are still made in one stage, and one 8-bit multiplier is about 31 levels deep. The adder that moved out was short. To go faster, the cut has to go inside the multiplier itself.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Put the register halfway through the code and the delay halves."
Delay is not spread evenly through the source lines. You must cut where the delay is, which needs a timing view, not a code view.
Source Measured: the run on this question, Yosys 0.70+290 (OSS CAD Suite 2026-11-02), slang front end, synth -flatten with ABC, ltp -noff
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ComparePipelining Versus Parallel CopiesL1 JuniorL2 Mid-Level
Compare pipelining a unit with building two copies of it that work in parallel.
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Reveal the Model Answer
Pipelining keeps one copy of the logic and adds registers, so it costs little area but adds latency. Two copies double the area and keep latency the same. But you need logic to split the work and merge the results in order. Pipelining needs the logic to be cut; parallel copies need the work to be independent.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Parallel copies are always better because latency does not grow."
They double area and power, and the splitter and merger add their own logic and ordering bugs. Choose by budget, not by habit.
Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 5.12 Arithmetic operators
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Prove ItSolve R4.5.1: A Two-Lane MAC on a Levels BudgetSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Break ItThe Valid Bit That Did Not Follow the DataL1 JuniorL2 Mid-Level
Asked if they forget the control signals
You pipelined the datapath by one stage. What breaks if the valid signal is not delayed too?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The valid bit now arrives one cycle before its data. The next block accepts a result that is still the previous one, and the last result has no valid at all. Every control bit that describes the data must pass through the same number of registers.
Two Data Stages, One Valid RegisterFive inputs with gaps. inis the sum the bench expects for the inputs offered at that edge.out_validrises one edge too early, every time.All cycles- Cycle 2
The first input, sum 10, is taken.
out_validis already 1, butsumstill holds 0 from before. The consumer counts 0. - Cycle 3
sumshows 10 now, one edge late. The consumer pairs it with the second input and is wrong again. - Cycle 5
After the gap the same thing: valid marks 100, the previous sum. Each result is the one before it.
- Cycle 9
The last input, 20, is counted with the word 1020. Five results, zero right.
Measured on the lab bench, one value per edge. The data went through two registers and valid through one.
Self-Check
Tick each key point you covered in your answer.
Missed Corner
"Valid only needs resetting; it is not part of the datapath."
Valid travels with its data. Data flops may skip reset, but the valid flops must be reset and must have the same latency.
Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 8.1.5.1 Non-resettable RTL flip-flop models
- Cycle 2
-
Prove ItSolve R4.3.1: An Adder Tree with Its Valid PipeSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Prove ItSolve R4.3.1: An Adder Tree with Its Valid PipeSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"Pipelining makes each result come out sooner."
Each result now crosses two registers instead of one. The twin checks the pipelined design for a one-cycle latency and no result matches.
Run It
The two-stage dot product, checked for a one-cycle latency, then for two cycles.
dot_pipe: results matching a latency of 1 cycle: 0 of 17 FAIL: pipelining did not make results arrive sooner; each one now takes two cyclesSee the Fix
// y = a0*b0 + a1*b1, 8-bit inputs. Pipelined: products in stage 1, the sum in stage 2.
module dot_pipe (
input logic clk,
input logic [7:0] a0, b0, a1, b1,
output logic [16:0] y
);
logic [15:0] p0, p1;
always_ff @(posedge clk) begin
p0 <= a0 * b0;
p1 <= a1 * b1;
y <= p0 + p1;
end
endmodule
module tb;
logic clk = 0;
always #5 clk = ~clk;
logic [7:0] a0 = 0, b0 = 0, a1 = 0, b1 = 0;
logic [16:0] y, hist[0:2];
int checked = 0, matched = 0;
int unsigned seed = 3;
dot_pipe dut (.clk(clk), .a0(a0), .b0(b0), .a1(a1), .b1(b1), .y(y));
initial begin
for (int i = 0; i < 20; i++) begin
@(posedge clk); #1;
// hist[k]: the result for the inputs applied k edges before the last one
if (i >= 3) begin checked++; if (y == hist[1]) matched++; end
hist[2] = hist[1]; hist[1] = hist[0];
a0 = $urandom(seed); b0 = $urandom(seed); a1 = $urandom(seed); b1 = $urandom(seed);
hist[0] = a0 * b0 + a1 * b1;
end
$display("dot_pipe: results matching a latency of 2 cycles: %0d of %0d", matched, checked);
if (matched == checked) $display("PASS: the pipelined design gives a new result every cycle, two cycles after its inputs");
$finish;
end
endmodule
Prints: dot_pipe: results matching a latency of 2 cycles: 17 of 17 PASS: the pipelined design gives a new result every cycle, two cycles after its inputs
Half-Truth
"Two stages means twice the clock frequency."
Only if the cut splits the delay in half. Here the multiplier alone is 31 of the 37 levels, so the measured gain is 6 levels.
Source Measured: the run on this question, Yosys 0.70+290 (OSS CAD Suite 2026-11-02), slang front end, synth -flatten with ABC, ltp -noff
Buzzword Without Mechanism
Answers "throughput goes up" without saying in what unit.
Per cycle, throughput is unchanged. Per second, it rises only with a faster clock. Mixing the two hides the real trade-off.