Interview Question · Concept
Synchronous vs Asynchronous Reset
- Likely at Qualcomm
The Question
The interviewer asks
What is the difference between a synchronous and an asynchronous reset? When would you choose each?
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Reveal the Model Answer
A synchronous reset is sampled at the clock edge like data. So it needs a running clock and a pulse that covers an edge. An asynchronous reset acts at once through the flop's reset pin, with no clock. Its assertion is easy; its release is the hard part, because it must meet recovery and removal times. Many ASICs use asynchronous assertion with a synchronized release.
- A sees the release in time
The release reaches A well before edge k. A leaves reset at edge k.
Follow the calls, values and waits
- data release: rst_n pin → Flop A
- B sees it inside its window
The release reaches B a moment before edge k, inside its recovery window: the short time before an edge in which a flop cannot take a reset change cleanly. B may leave reset at edge k or k+1, or sit metastable, hovering between 0 and 1, for a while.
Follow the calls, values and waits
- data release: rst_n pin → Flop B
- The handshake hangs
A is ready at edge k and B at edge k+1. Logic that expected both in the same cycle waits for an event that already passed.
Follow the calls, values and waits
- data ready: Flop A → Handshake
- data ready: Flop B → Handshake
Read the diagram as text
- rst_n pin: released near edge k
- clk: edge k, then k+1
- Flop A: near the pin
- Flop B: far end of the wire
- Handshake: needs A and B ready together
- rst_n pin → Flop A: short wire
- rst_n pin → Flop B: long wire
- clk → Flop A
- clk → Flop B
- Flop A → Handshake: ready
- Flop B → Handshake: ready
Drawn from the timing rules, not from a simulation. A zero-delay RTL simulation releases every flop at the same instant.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer writes both flop templates. It says which one needs the clock running to reset.
What Interviewers Listen For (Mid-Level)
A good mid-level answer talks about the release, not the assertion. It names recovery and removal times, and the reset synchronizer that makes the release safe.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompare
- Synchronous vs Asynchronous Reset
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WhyRecovery and Removal TimesL1 JuniorL2 Mid-Level
Why is the release of an asynchronous reset the dangerous part? Explain recovery and removal.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Recovery time is how long before a clock edge the reset must be released. Removal time is how long after the edge it must stay asserted. They are the setup and hold of the reset pin. If the release lands inside that window, the flop may go metastable or leave reset one cycle late.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Reset timing does not matter, because reset happens only at power-up."
Every release is a timing event. A release that violates recovery can start some flops a cycle before others, at every reset.
Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 8.1.5.6 Asynchronous reset metastability synchronizers
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What IfTwo Counters That Leave Reset ApartL2 Mid-Level
What if two counters that must always match leave reset on different clock edges?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
They now differ by one count forever, and nothing brings them back together. The cause is a raw asynchronous release. It reached one counter before an edge and the other just after it. A reset synchronizer releases both on the same edge, because its output changes only at a clock edge.
Self-Check
Tick each key point you covered in your answer.
Tool as Truth
"RTL simulation would have shown the offset."
Zero-delay RTL releases every flop at the same instant. The skew between reset wires exists only in the real circuit.
Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 8.1.5.6 Asynchronous reset metastability synchronizers
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Prove ItSolve R2.2.1: The Counter That Started EarlySimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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CompareWhat a Synchronous Reset CostsL1 JuniorL2 Mid-Level
Compare the costs. What does a synchronous reset add to the design, and what does it give you?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A synchronous reset is extra logic in front of D, such as an AND or a mux. Some libraries have flops with a synchronous reset input instead. It sits on the data path, so it can touch timing. In return, it filters short glitches on the reset line, and its release is just data, timed like any other path.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"A synchronous reset is free."
It needs gating in front of each flop or a special flop. It also needs the reset to be wide enough to cover a clock edge.
Source Cummings, Mills and Golson, Asynchronous & Synchronous Reset Design Techniques - Part Deux (SNUG Boston 2003) §4.2 and 4.3
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Prove ItSolve R2.2.1: The Counter That Started EarlySimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Missed Corner
"A synchronous reset works like an asynchronous one, just one edge later."
With no clock there is no edge, so a synchronous reset does nothing. The twin stops the clock and pulses reset; the count stays.
Run It
A counter with a synchronous reset, reset while the clock is stopped, then the asynchronous form.
count before reset: 4 q during reset with no clock: 4 FAIL: a synchronous reset needs a clock edge; q kept its countSee the Fix
module cnt (input logic clk, rst, output logic [3:0] q);
always_ff @(posedge clk or posedge rst) // asynchronous reset
if (rst) q <= 4'd0;
else q <= q + 4'd1;
endmodule
module tb;
logic clk = 0, rst = 1, run = 1; logic [3:0] q;
cnt dut (.clk(clk), .rst(rst), .q(q));
always #5 if (run) clk = ~clk;
initial begin
#12 rst = 0; // start-up reset, released after one edge
#40 run = 0; // the clock is gated off; q holds a count
$display("count before reset: %0d", q);
#10 rst = 1; #20; // reset pulses while there is no clock
$display("q during reset with no clock: %0d", q);
if (q === 4'd0) $display("PASS: q cleared at once, with no clock");
$finish;
end
endmodule
Prints: count before reset: 4 q during reset with no clock: 0 PASS: q cleared at once, with no clock
Misconception
"An asynchronous reset needs no synchronizer, because it does not use the clock."
Assertion needs no clock, but release does. A release close to an edge can make a flop metastable, or let flops leave reset in different cycles.
Source Cummings, Mills and Golson, Asynchronous & Synchronous Reset Design Techniques - Part Deux (SNUG Boston 2003) §5.3, 5.4 and 6
Buzzword Without Mechanism
"Asynchronous reset is better because it is faster."
"Faster" names no mechanism. The real points are: it works without a clock, it keeps reset logic off the data path, and its release needs care.