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Interview Question · Concept

Timing-Closure Judgement

L3 SeniorL4 Stafftimingtiming closuresdc
  • Likely at Synopsys
  • Likely at Qualcomm

The interviewer asks

Two weeks before tape-out, one path in your block misses by 8% at the slow corner. Physical design asks for a multicycle exception. How do you decide?

Reveal the Model Answer

An exception is legal only if the design already gives the path two cycles. The source must hold its value and the capture must happen every other cycle. If it does not, the exception hides a real bug from timing. Otherwise, weigh an RTL fix and its re-verification against physical fixes, or a spec change such as a lower clock. Write down who signed off the exception and why.

A Two-Cycle DatapathArrows are signals. en is 1 every second cycle, so a changes only every second edge.
A two-cycle datapathArrows are signals. `en` is 1 every second cycle, so `a` changes only every second edge. component en_reg toggles every edge component a0_reg, a1_reg edfxtp_1, load whenen component u0 (nand2_1) short path component u1-u6 (xor2_1) long path component y0_reg, y1_reg edfxtp_1, load whenen DEa0a0, a1D of y0D of y1DE
Read the diagram as text
  • en_reg: toggles every edge
  • a0_reg, a1_reg: edfxtp_1, load when en
  • u0 (nand2_1): short path
  • u1-u6 (xor2_1): long path
  • y0_reg, y1_reg: edfxtp_1, load when en
  • en_reg → a0_reg, a1_reg: DE
  • a0_reg, a1_reg → u0 (nand2_1): a0
  • a0_reg, a1_reg → u1-u6 (xor2_1): a0, a1
  • u0 (nand2_1) → y0_reg, y1_reg: D of y0
  • u1-u6 (xor2_1) → y0_reg, y1_reg: D of y1
  • en_reg → y0_reg, y1_reg: DE

Both ends load on the same enable, so data has two periods from launch to capture.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Senior)

A good senior answer asks how often the capture flop loads before answering. It refuses the exception unless the RTL or an assertion proves two cycles.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyBreak ItCompareScale It

  1. Timing-Closure Judgement
  2. WhyProving a Multicycle Path Is RealL2 Mid-LevelL3 Senior

    Why should a multicycle exception come with an assertion?

    Reveal the Model Answer

    The exception is a promise that the source stays stable for two cycles before each capture. Only the RTL keeps that promise, and RTL changes later. So write an assertion: the source is stable at every capture edge. Simulation or formal tools then check the promise on every change.

    Self-Check

    Tick each key point you covered in your answer.

    Delivery

    "The designer who wrote the RTL knows it is a multicycle path."

    The next person to edit the block may not. Without a check, a later change silently breaks the exception, and timing still passes.

  3. Break ItA False Path on a Real PathL2 Mid-LevelL3 Senior

    How can a wrong timing exception get through to silicon?

    Reveal the Model Answer

    A broad false path, such as one on all inputs, also removes paths that do matter. STA then reports them as unconstrained, not as failing. If nobody reads the unconstrained-endpoint list, the paths are never timed. Gate-level simulation without delays will not catch it either.

    Self-Check

    Tick each key point you covered in your answer.

    Missed Corner

    "If timing is clean, all paths met timing."

    Clean only covers the paths that were checked. Unconstrained endpoints are silent unless you ask the tool to list them.

    Source Lesson L2.8 review claims (set_false_path -from [all_inputs] leaves unconstrained endpoints, measured with OpenSTA)

  4. CompareRTL Fix, Physical Fix or Spec ChangeL3 SeniorL4 Staff

    Compare the three ways out of a late timing miss: change the RTL, push physical design harder, or change the spec.

    Reveal the Model Answer

    An RTL change fixes the cause but restarts verification and synthesis. A physical fix keeps the RTL frozen, but it may cost area, power or days of runs, and may not converge. A spec change may be cheapest if the system can absorb it. Examples are a lower clock or one more cycle of latency. The choice depends on margin, schedule and who owns each risk.

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "Never change RTL this late."

    A small, well-checked RTL change with an equivalence run can be lower risk than weeks of physical iterations. The rule should be a cost comparison, not a ban.

    Source Kahng, Lienig, Markov and Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, ch. 8 (timing closure), as cited in lesson L2.9

  5. Scale ItReviewing Timing Exceptions Across a ChipL3 SeniorL4 Staff

    How would you run timing-exception review for a whole SoC?

    Reveal the Model Answer

    Keep every exception in one reviewed file, each with an owner, a reason and a proof such as an assertion. Block owners sign off their exceptions before integration. Run constraint checks on each release for unconstrained endpoints and overlapping exceptions. Re-review all exceptions when the RTL of their block changes.

    Self-Check

    Tick each key point you covered in your answer.

    Wrong Altitude

    "Physical design owns the SDC, so they own the exceptions."

    Only the RTL owner knows whether a path really has two cycles or never toggles. The PD team can apply an exception; they cannot prove it.

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"Declare a multicycle path; the logic has time to settle."

The constraint only changes what the timing tool checks. The flop still captures every cycle, so the twin catches wrong values on every edge.

Run It

A 1500 ps path at a 1000 ps clock: a constraint only, then enables in the RTL.

RUNIcarus Verilog · in your browser
Edit the code, then run it

        
Expected: multicycle constraint only: captures=40 wrong=39 FAIL: the constraint changed the timing report, not the logic; the flop still captures every cycle

        
        
      

      
See the Fix
`timescale 1ps/1ps
// A 4-bit value crosses 1500 ps of logic. The clock period is 1000 ps.
module mcp #(parameter bit EVERY_OTHER = 0) ();
  logic clk = 0, phase = 0;
  logic [3:0] src = 0, d = 0;
  int captures = 0, wrong = 0;
  always #500 clk = ~clk;
  always @(posedge clk) begin
    phase <= #100 ~phase;
    if (!EVERY_OTHER || phase) src <= #100 src + 1;   // launch flop (clock-to-Q 100 ps)
  end
  always @(src) d <= #1500 src;                        // the slow logic
  always @(posedge clk)                                // capture flop: has the launched value arrived?
    if (!EVERY_OTHER || phase) begin
      captures++;
      if (d !== src) wrong++;
    end
endmodule
module tb;
  // The fix: the design itself launches and captures on every other edge,
  // so the logic really has two periods. Then the 2-cycle constraint is true.
  mcp #(.EVERY_OTHER(1)) dut ();
  initial begin
    #40000;
    $display("enable every other edge: captures=%0d wrong=%0d", dut.captures, dut.wrong);
    if (dut.wrong == 0) $display("PASS: with launch and capture enabled every other edge, every capture is right");
    $finish;
  end
endmodule

Prints: enable every other edge: captures=20 wrong=0 PASS: with launch and capture enabled every other edge, every capture is right

    

  

    
Wrong Altitude

    
A staff-level answer that only lists cell upsizing and buffering.

    
At this level the question is a decision: risk, schedule, who verifies the exception, and whether the spec can move. Listing tool tricks misses it.

  

    
Misconception

    
"A false path is safer than a multicycle path because the tool stops worrying."

    
A false path removes all timing on it, including hold. If the path is real at all, nothing checks it any more.

    
Source OpenSTA 3.1.0 command reference (set_multicycle_path, set_false_path), as cited in lesson L2.8

  

    
Learn It, Then Prove It