Interview Question · Debug

A Path with Negative Slack

L1 JuniorL2 Mid-Leveltimingstatiming closuredebug

The interviewer asks

Synthesis gives you this report for your scaling block at 500 MHz. Walk through what you check, and in what order, before you change anything.

log

Illustrative report (invented numbers), clock core_clk, period 2.00 ns
Startpoint: u_scale/a_q[3] (rising edge-triggered flip-flop clocked by core_clk)
Endpoint:   u_scale/r_q[15] (rising edge-triggered flip-flop clocked by core_clk)
  Point                                   Incr      Path
  clock core_clk (rise edge)              0.00      0.00
  u_scale/a_q[3]/CK -> Q                  0.21      0.21
  u_scale/mul_0/... (24 cells)            0.95      1.16
  u_scale/mul_1/... (22 cells)            0.88      2.04
  u_scale/r_q[15]/D                                 2.04
  data arrival time                                 2.04
  clock core_clk (rise edge)              2.00      2.00
  library setup time                     -0.06      1.94
  data required time                                1.94
  slack (VIOLATED)                                 -0.10

Reveal the Model Answer

First, check the path is real: right clock, right period, no missing false path or multicycle intent. Next, read where the time goes. Here two multipliers in series take most of the 2 ns, so logic depth is the problem. Small misses can go to the tool: better cells, or restructuring. A miss in two chained multipliers usually needs an RTL change, such as a register between them.

Timing pathStage A Misses the ClockFlop a0 launches, the middle register r1 captures; six xor2_1 cells sit between them. The clock is ideal: every flop sees the edge at 0 ns.

a1 → r1setup check, latest arrival7 cells

Clock latency
Cell delay
Setup time

A long stage
Clock-to-Q and six XOR gates: the data arrives at 1.4819 ns.
The next edge
r1 samples at 1.25 ns, less its setup time: required at 1.1404 ns.
Violated
The data comes too late for this edge, and the slack is -0.3415 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 1.2500 ns, latency 0.0000 ns, library setup time −0.1096 ns.

Arrival 1.4819 ns, required 1.1404 ns, slack −0.3415 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`a1/CLK` → `a1/Q`	dfxtp_1	rise	0.4872	0.4872	0.2741
	`a1/Q` → `m1/B`	wire qa1	rise	0.0000	0.4872	0.2741
2	`m1/B` → `m1/X`	xor2_1	fall	0.1173	0.6045	0.0897
	`m1/X` → `m2/A`	wire s1	fall	0.0000	0.6045	0.0897
3	`m2/A` → `m2/X`	xor2_1	fall	0.1781	0.7827	0.0897
	`m2/X` → `m3/A`	wire s2	fall	0.0000	0.7827	0.0897
4	`m3/A` → `m3/X`	xor2_1	fall	0.1781	0.9608	0.0897
	`m3/X` → `m4/A`	wire s3	fall	0.0000	0.9608	0.0897
5	`m4/A` → `m4/X`	xor2_1	fall	0.1781	1.1389	0.0897
	`m4/X` → `m5/A`	wire s4	fall	0.0000	1.1389	0.0897
6	`m5/A` → `m5/X`	xor2_1	fall	0.1781	1.3170	0.0897
	`m5/X` → `m6/A`	wire s5	fall	0.0000	1.3170	0.0897
7	`m6/A` → `m6/X`	xor2_1	fall	0.1649	1.4819	0.0723
	`m6/X` → `r1/D`	wire s6	fall	0.0000	1.4819	0.0723

The report

Startpoint: a1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: stageA
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ a1/CLK (sky130_fd_sc_hd__dfxtp_1)
     7    0.0286    0.2741    0.4872    0.4872 ^ a1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 qa1 (net)
                    0.2741    0.0000    0.4872 ^ m1/B (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1173    0.6045 v m1/X (sky130_fd_sc_hd__xor2_1)
                                                 s1 (net)
                    0.0897    0.0000    0.6045 v m2/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    0.7827 v m2/X (sky130_fd_sc_hd__xor2_1)
                                                 s2 (net)
                    0.0897    0.0000    0.7827 v m3/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    0.9608 v m3/X (sky130_fd_sc_hd__xor2_1)
                                                 s3 (net)
                    0.0897    0.0000    0.9608 v m4/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    1.1389 v m4/X (sky130_fd_sc_hd__xor2_1)
                                                 s4 (net)
                    0.0897    0.0000    1.1389 v m5/A (sky130_fd_sc_hd__xor2_1)
     1    0.0042    0.0897    0.1781    1.3170 v m5/X (sky130_fd_sc_hd__xor2_1)
                                                 s5 (net)
                    0.0897    0.0000    1.3170 v m6/A (sky130_fd_sc_hd__xor2_1)
     1    0.0017    0.0723    0.1649    1.4819 v m6/X (sky130_fd_sc_hd__xor2_1)
                                                 s6 (net)
                    0.0723    0.0000    1.4819 v r1/D (sky130_fd_sc_hd__dfxtp_1)
                                        1.4819   data arrival time

                    0.1000    1.2500    1.2500   clock clk (rise edge)
                              0.0000    1.2500   clock network delay (ideal)
                              0.0000    1.2500   clock reconvergence pessimism
                                        1.2500 ^ r1/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.1096    1.1404   library setup time
                                        1.1404   data required time
-------------------------------------------------------------------------------------
                                        1.1404   data required time
                                       -1.4819   data arrival time
-------------------------------------------------------------------------------------
                                       -0.3415   slack (VIOLATED)

Measured in lesson L5.4 on a different path. Clock-to-Q and six XOR gates arrive 0.3415 ns too late: read where the time goes first.

Self-Check

Tick each key point you covered in your answer.

Key point 1 First, check the path is real: right clock, right period, no missing false path or multicycle intent. Key point 2 Next, read where the time goes. Key point 3 Here two multipliers in series take most of the 2 ns, so logic depth is the problem. Key point 4 Small misses can go to the tool: better cells, or restructuring. Key point 5 A miss in two chained multipliers usually needs an RTL change, such as a register between them.

What Interviewers Listen For (Junior)

A good junior answer reads the startpoint, endpoint, arrival, required time and slack aloud. It spots the two multipliers as the big numbers.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

A Path with Negative Slack
WhyLevels of Logic as a Timing EstimateL1 JuniorL2 Mid-Level
Why do RTL designers talk about "levels of logic" before any real timing exists?

Reveal the Model Answer

Levels of logic count the gates on the longest path between two flops. Before placement there are no real wire delays, so the count is a quick and stable estimate. A team can set a budget, such as 20 levels at the target clock, and catch deep paths in RTL review.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Levels of logic count the gates on the longest path between two flops. Key point 2 Before placement there are no real wire delays, so the count is a quick and stable estimate. Key point 3 A team can set a budget, such as 20 levels at the target clock, and catch deep paths in RTL review.

Half-Truth

"Fewer levels always means a faster path."

Levels ignore wire length, fanout and cell strength. A path with few levels but long wires can be slower. Levels are a budget, not a sign-off number.

Source Kahng, Lienig, Markov and Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, ch. 8 (timing closure), as cited in lesson L2.9
- Lesson R4.1Clock Period, Setup and Hold in One Picture
- Lesson R4.5Multipliers, MACs and the Long Path
Prove ItSolve R4.5.1: A Two-Lane MAC on a Levels BudgetSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem R4.5.1
CompareLetting the Tool Fix It Versus Changing the RTLL2 Mid-Level
Compare leaving a failing path to the synthesis and place-and-route tools with fixing it in RTL.

Reveal the Model Answer

Tools can upsize cells, restructure logic and buffer long wires, and that often closes small misses. They cannot change the cycle-level design: a register that is not in the RTL stays absent. When the miss is large or repeats after each tool run, an RTL change is cheaper than many tool runs.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Tools can upsize cells, restructure logic and buffer long wires, and that often closes small misses. Key point 2 They cannot change the cycle-level design: a register that is not in the RTL stays absent. Key point 3 When the miss is large or repeats after each tool run, an RTL change is cheaper than many tool runs.

Tool as Truth

"The tool will retime it for us."

Retiming is an option some tools offer, and many flows leave it off. Verification, equivalence and debug all get harder when registers move. Check before relying on it.

Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 5.12 Arithmetic operators
- Lesson R4.6Where the Register Goes: Retiming by Hand
What IfEquivalence Checking a Retimed NetlistL2 Mid-LevelL3 Senior
Asked if they say the tool can retime

What if the synthesis tool does retime registers? What changes for the rest of the flow?

Reveal the Model Answer

The netlist no longer has one flop for each RTL flop. A normal RTL-to-netlist equivalence check matches flops one to one, so it reports a mismatch. You then need sequential equivalence, which compares only the outputs over time, and it is slower. Waveform debug also gets harder, because RTL register names no longer exist in the netlist.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The netlist no longer has one flop for each RTL flop. Key point 2 A normal RTL-to-netlist equivalence check matches flops one to one, so it reports a mismatch. Key point 3 You then need sequential equivalence, which compares only the outputs over time, and it is slower. Key point 4 Waveform debug also gets harder, because RTL register names no longer exist in the netlist.

Misconception

"Equivalence checking proves any synthesized netlist, so retiming costs nothing."

The common check is state-matching: it assumes each RTL flop has a matching netlist flop. Moved registers break that assumption.

Source Seligman, Schubert and Kiran Kumar, Formal Verification (2nd ed., 2023) ch. 8 Types of equivalence to check: combinational and sequential equivalence
Prove ItSolve R4.7.1: A Pipelined CRC EngineSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem R4.7.1
Scale ItThousands of Failing PathsL2 Mid-LevelL3 Senior
The report shows 4000 failing paths, not one. How do you work through them?
2:30

You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.

Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
Reveal the Model Answer

Group the paths by start and end block and by cause. Often a few root causes explain most of them, such as one high-fanout signal, one bad constraint or one deep block. Fix the worst groups, then rerun and track WNS (the worst negative slack) and TNS (the sum of all negative slack).

Measured sweepSetup Slack at Every Flop of the MAC, Complete SDCOne OpenSTA run with each of the 52 flop D pins in its own path group, in register order.

Endpoint flop (ra, rb, p, acc) 0setup slack = 13.2 ps
The input registers ra and rb load a and b but also obey en: slack 0.0132 ns.
Endpoint flop (ra, rb, p, acc) 51setup slack = -468.8 ps
The worst endpoint, acc[19]: -0.4688 ns. That is the WNS.
Endpoint flop (ra, rb, p, acc) 51setup slack = -468.8 ps
12 of 52 endpoints fail, in p and acc. Their negative slacks add up to about -2.172 ns: the TNS.

Read the plot as a table
Endpoint flop (ra, rb, p, acc) setup slack
0 13.2 ps
10 13.2 ps
20 -39 ps
30 115 ps
40 185.1 ps
50 -435.9 ps
51 -468.8 ps

OpenSTA 3.1.0 on the 447-cell MAC, 5 ns ideal clock, no wires.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Group the paths by start and end block and by cause. Key point 2 Often a few root causes explain most of them, such as one high-fanout signal, one bad constraint or one deep block. Key point 3 Fix the worst groups, then rerun and track WNS (the worst negative slack) and TNS (the sum of all negative slack).
Delivery

Fixes paths one by one from the top of the list.

Many paths share a cause. Fixing the shared signal or constraint clears hundreds at once; fixing paths one at a time does not converge.
- Lesson L2.5Reading a Timing Report

Endpoint flop (ra, rb, p, acc)	setup slack
0	13.2 ps
10	13.2 ps
20	-39 ps
30	115 ps
40	185.1 ps
50	-435.9 ps
51	-468.8 ps

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"Add another register after the adder; more pipelining fixes timing."

A register after the whole cloud leaves both multipliers between two flops. Only a register inside the cloud shortens the path. The twin measures 55 levels against 30.

Run It

Two multipliers in series, with the new register after both (twin) or between them (fix).

// y = (top byte of a * b) * c, with two register stages after the input registers.
module scale_out (
  input  logic        clk,
  input  logic [7:0]  a, b, c,
  output logic [15:0] y
);
  logic [7:0] a_q, b_q, c_q;
  logic [15:0] r_q;                          // the new register sits after both multipliers
  always_ff @(posedge clk) begin
    a_q <= a; b_q <= b; c_q <= c;
    r_q <= 8'(16'(a_q * b_q) >> 8) * c_q;
    y   <= r_q;
  end
endmodule

See the Fix

// y = (top byte of a * b) * c, with two register stages after the input registers.
module scale_mid (
  input  logic        clk,
  input  logic [7:0]  a, b, c,
  output logic [15:0] y
);
  logic [7:0] a_q, b_q, c_q;
  logic [7:0] p_q, c_q2;                     // the new register sits between the two multipliers
  always_ff @(posedge clk) begin
    a_q <= a; b_q <= b; c_q <= c;
    p_q  <= 8'(16'(a_q * b_q) >> 8);
    c_q2 <= c_q;
    y    <= p_q * c_q2;
  end
endmodule

Delivery

Starts rewriting the ALU before checking the clock definition.

A wrong period, a missing clock relation or a path that should be a false path gives a real-looking report. Fixing RTL for a wrong constraint wastes days.

Half-Truth

"Negative slack means the chip will fail."

Slack is measured against the constraints and one corner. The path may be a false path, or the constraint may be too tight. A real miss at sign-off corners does fail.

Source Kahng, Lienig, Markov and Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, ch. 8 (timing closure), as cited in lesson L2.9

Find Your Next Track

Put Your Skills to Work

Prepare to Explain Your Thinking

An Idea to Try? Pick a Tool.

A Path with Negative Slack

Your Answer

Self-Check

What Interviewers Listen For (Junior)

What Interviewers Listen For (Mid-Level)

Cross-Questions

Your Answer

Self-Check

Your Answer

Self-Check

Your Answer

Self-Check

Your Answer

Self-Check

What People Get Wrong

Learn It, Then Prove It

The Question

Your Answer

Self-Check

What Interviewers Listen For (Junior)

What Interviewers Listen For (Mid-Level)

Cross-Questions

Your Answer

Self-Check

Your Answer

Self-Check

Your Answer

Self-Check

Your Answer

Self-Check

What People Get Wrong

Learn It, Then Prove It