Interview Question · Code Reading
Multicycle Paths and the Hold Edge
- Likely at Qualcomm
The Question
The interviewer asks
A slow datapath updates every other cycle, so someone adds the exception at the end of this SDC. Setup now passes. What else changed?
create_clock -name clk -period 1.0 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_input_delay 0.2 -clock clk [delete_from_list [all_inputs] [get_ports clk]]
set_multicycle_path 2 -setup -from [get_cells {a0_reg a1_reg}] -to [get_cells {y0_reg y1_reg}]You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The hold check moved too. Hold is checked one edge before the setup capture edge. So moving setup to the second edge moves hold to the first, a full period later than intended. Now hold fails. Pair -setup 2 with -hold 1 to put hold back at the launch edge. Then prove in simulation that the data really is stable for two cycles, because STA trusts the exception.
a at edge 0. A 1 marks the edge each check uses.- Cycle 0
By default, setup is checked at edge 1 and hold at edge 0, the launch edge itself.
- Cycle 1
With
-setup 2alone, hold moves to edge 1. D0 must stay stable for a whole period after launch. - Cycle 2
Setup is at edge 2, where
yloads.-hold 1brings hold back from edge 1 to edge 0.
Edges 0 to 3 of the 1 ns clock, with the edge each check uses marked as a 1.
a0_reg launches; y0_reg captures after one nand2_1. Both are enable flops on the same en.a0_reg → y0_reghold check, earliest arrival2 cells
- Clock latency
- Cell delay
- Hold time
- Fast data
Clock-to-Q and one gate: the new value reaches
y0_regat 0.5642 ns. - A hold edge one period late
The hold check now uses the edge at 1 ns, not 0 ns. Required after 0.9031 ns.
- Violated
Slack -0.3389 ns: the data would have to stay put for most of a period.
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 1.0000 ns, latency 0.0000 ns, library hold time −0.0969 ns.
Arrival 0.5642 ns, required 0.9031 ns, slack −0.3389 ns (violated).
| Cell | Arc | Through | Edge | Delay (ns) | Time (ns) | Slew (ns) |
|---|---|---|---|---|---|---|
| 1 | a0_reg/CLK → a0_reg/Q | edfxtp_1 | fall | 0.4802 | 0.4802 | 0.1478 |
a0_reg/Q → u0/A | wire a0 | fall | 0.0000 | 0.4802 | 0.1478 | |
| 2 | u0/A → u0/Y | nand2_1 | rise | 0.0840 | 0.5642 | 0.0363 |
u0/Y → y0_reg/D | wire s0 | rise | 0.0000 | 0.5642 | 0.0363 |
The report
Startpoint: a0_reg (rising edge-triggered flip-flop clocked by clk)
Endpoint: y0_reg (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Fanout Cap Slew Delay Time Description
-------------------------------------------------------------------------------------
0.1000 0.0000 0.0000 clock clk (rise edge)
0.0000 0.0000 clock network delay (ideal)
0.1000 0.0000 0.0000 ^ a0_reg/CLK (sky130_fd_sc_hd__edfxtp_1)
5 0.0190 0.1478 0.4802 0.4802 v a0_reg/Q (sky130_fd_sc_hd__edfxtp_1)
a0 (net)
0.1478 0.0000 0.4802 v u0/A (sky130_fd_sc_hd__nand2_1)
1 0.0019 0.0363 0.0840 0.5642 ^ u0/Y (sky130_fd_sc_hd__nand2_1)
s0 (net)
0.0363 0.0000 0.5642 ^ y0_reg/D (sky130_fd_sc_hd__edfxtp_1)
0.5642 data arrival time
0.1000 1.0000 1.0000 clock clk (rise edge)
0.0000 1.0000 clock network delay (ideal)
0.0000 1.0000 clock reconvergence pessimism
1.0000 ^ y0_reg/CLK (sky130_fd_sc_hd__edfxtp_1)
-0.0969 0.9031 library hold time
0.9031 data required time
-------------------------------------------------------------------------------------
0.9031 data required time
-0.5642 data arrival time
-------------------------------------------------------------------------------------
-0.3389 slack (VIOLATED)The short path with only -setup 2: hold is now checked one period late, and fails by 0.3389 ns.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says the exception moves the setup check to the second edge. It adds that hold needs its own -hold setting.
What Interviewers Listen For (Senior)
A good senior answer draws the launch and capture edges for both checks. It insists on an enable that makes the exception true, and asks for an assertion that proves it.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompare
- Multicycle Paths and the Hold Edge
-
WhyWhy Hold Follows the Setup EdgeL1 JuniorL2 Mid-Level
Why does moving the setup capture edge also move the hold check?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The tool defines the hold check relative to the setup relationship. One capture edge earlier, it checks that the next launch does not overwrite what the setup capture edge should catch. Move setup to edge two and that earlier edge becomes edge one.
-hold 1pulls the hold check back by one cycle to the launch edge.Timing pathHold of the Short Path with Both Multipliers Whole patha0_reg → y0_reghold check, earliest arrival2 cells
- Clock latency
- Cell delay
- Hold time
- Back at the launch edge
The hold edge is back at 0 ns, the edge that launched the data.
- Met
Slack 0.6611 ns: this is the normal hold check of a path launched and captured on one edge.
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 0.0000 ns, latency 0.0000 ns, library hold time −0.0969 ns.
Arrival 0.5642 ns, required −0.0969 ns, slack 0.6611 ns (met).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 a0_reg/CLK→a0_reg/Qedfxtp_1 fall 0.4802 0.4802 0.1478 a0_reg/Q→u0/Awire a0 fall 0.0000 0.4802 0.1478 2 u0/A→u0/Ynand2_1 rise 0.0840 0.5642 0.0363 u0/Y→y0_reg/Dwire s0 rise 0.0000 0.5642 0.0363 The report
Startpoint: a0_reg (rising edge-triggered flip-flop clocked by clk) Endpoint: y0_reg (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.1000 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.1000 0.0000 0.0000 ^ a0_reg/CLK (sky130_fd_sc_hd__edfxtp_1) 5 0.0190 0.1478 0.4802 0.4802 v a0_reg/Q (sky130_fd_sc_hd__edfxtp_1) a0 (net) 0.1478 0.0000 0.4802 v u0/A (sky130_fd_sc_hd__nand2_1) 1 0.0019 0.0363 0.0840 0.5642 ^ u0/Y (sky130_fd_sc_hd__nand2_1) s0 (net) 0.0363 0.0000 0.5642 ^ y0_reg/D (sky130_fd_sc_hd__edfxtp_1) 0.5642 data arrival time 0.1000 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.0000 0.0000 clock reconvergence pessimism 0.0000 ^ y0_reg/CLK (sky130_fd_sc_hd__edfxtp_1) -0.0969 -0.0969 library hold time -0.0969 data required time ------------------------------------------------------------------------------------- -0.0969 data required time -0.5642 data arrival time ------------------------------------------------------------------------------------- 0.6611 slack (MET)The same short path with
-setup 2and-hold 1: hold is back at the launch edge and passes.Self-Check
Tick each key point you covered in your answer.
-
CompareFalse Path vs Multicycle PathL1 JuniorL2 Mid-Level
Compare a false path with a multicycle path. When is each the right exception?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A false path removes paths from timing entirely. It is for signals that can never propagate in one cycle in practice, such as static configuration written before use. A multicycle path keeps the check but gives it N cycles, for data that is guaranteed stable for N cycles. A false path is the riskier promise, because a wrong one hides a real path forever; never false-path a reset release.
Self-Check
Tick each key point you covered in your answer.
-
What IfA Configuration Register Written While RunningL2 Mid-Level
What if software writes the false-pathed configuration register while the block is running?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Then the false path is no longer true. The new value can reach a capture flop in any cycle, untimed. Some bits may then be caught a cycle late or go metastable. Either forbid writes while the block runs, and check that rule with an assertion. Or time the path for real.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"It is a configuration register, so it is always a false path."
The exception holds only if software writes it before use. A write in mission mode makes the path real.
Source Lesson L2.8 key points
-
Break ItA Multicycle Path Whose Enable DisappearedL2 Mid-LevelL3 Senior
An ECO removes the enable that made the datapath update every other cycle, but the exception below stays in the SDC. What happens, and who catches it?
sdc set_multicycle_path 2 -setup -from [get_cells {a0_reg a1_reg}] -to [get_cells {y0_reg y1_reg}] set_multicycle_path 1 -hold -from [get_cells {a0_reg a1_reg}] -to [get_cells {y0_reg y1_reg}]2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
STA still gives the path two cycles and reports it clean, while the silicon now captures every cycle and fails. The exception is a promise only the design can keep, so the check belongs in verification. The check is an assertion that the enable alternates and the source is stable at every capture edge. Rerunning that assertion after every ECO catches the broken promise.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve L2.8.1: Restore the Same-Edge Hold CheckSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"-setup 2 gives the path two cycles; nothing else moves."
The hold check follows the setup edge, so with -setup 2 alone hold lands one period late and fails at -0.3389 ns. Adding -hold 1 restores it.
Run It
The two-cycle datapath from lesson L2.8 with -setup 2 only.
create_clock -name clk -period 1.0 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_input_delay 0.2 -clock clk [delete_from_list [all_inputs] [get_ports clk]]
set_multicycle_path 2 -setup -from [get_cells {a0_reg a1_reg}] -to [get_cells {y0_reg y1_reg}]
Prints: 0.2419 slack (MET) -0.3389 slack (VIOLATED)
See the Fix
create_clock -name clk -period 1.0 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_input_delay 0.2 -clock clk [delete_from_list [all_inputs] [get_ports clk]]
set_multicycle_path 2 -setup -from [get_cells {a0_reg a1_reg}] -to [get_cells {y0_reg y1_reg}]
set_multicycle_path 1 -hold -from [get_cells {a0_reg a1_reg}] -to [get_cells {y0_reg y1_reg}]
Prints: 0.2419 slack (MET)
Half-Truth
"Multicycle paths are just a way to make setup pass."
A multicycle path is a promise about the design: the data changes only every N cycles. Without an enable that enforces it, the chip fails while STA reports clean.
Source ASIC Point lesson L2.8