Signoff Interview Questions

Overflow concentrated in one place, with low usage overall, points to a local cause. Here that cause is the channel, not a block that is too full. Look at where the demand comes from. It may be nets crossing the channel, pin access at the macro edges, or straps that took the tracks. The fixes act on that cause: a wider channel, pins turned away from it, or a different halo (keep-out ring). Each fix is measured by routed wirelength and timing, not by overflow alone.

Global routing plans each net through coarse tiles and counts tracks per tile edge. That says nothing about how a wire reaches a pin or which vias fit. Detailed routing picks real tracks, vias and pin access under width, spacing, area and enclosure rules. It can run out of iterations and leave violations in a readable layout, so its own count matters too.

Not necessarily. The router checks the rules it knows from the technology LEF, a subset of the foundry deck. Full DRC on the merged layout, with cells, fill and every rule, is a separate run. Antenna checking is separate again. Sign-off quotes which checker ran with which deck.

Density and routability-driven placement spread cells. That helps when demand comes from local crowding. It does nothing for nets that must cross a fixed gap. Floorplan fixes, such as macro position, channel width or pin edges, change where the nets go. Density changes distances but not the netlist's connectivity, so a connectivity hot spot needs the floorplan answer.

Start cheap and local: lower the target density or turn on routability-driven placement, which inflates cells in crowded regions. Then look at the cause, such as a pin cluster, a wide multiplexer or a macro channel. Fix that cause with a pin plan or floorplan change. Lower utilization is the expensive last resort. Re-check timing after each step, because spreading costs wire.

Routability-driven placement adds room only where the router predicts overflow. Lower utilization grows the whole block, so area and wire grow everywhere. The local fix keeps the dense, short-wired regions that had no problem. So it is the cheaper first step.

Coupling capacitance between neighbouring wires disturbs a quiet victim with a noise glitch, which can flip a latch. Or it changes the delay of a switching victim. If the aggressor switches the opposite way, the effective coupling load grows and the victim slows, hurting setup. If it switches the same way the victim speeds up, which can break hold. Real analysis needs timing windows and activity, so uniform coupling factors are only a sensitivity check.

The current through a capacitor follows the rate of change of the voltage across it. If both wires move the same way, the voltage across the coupling capacitor barely changes and it draws little current. If they move in opposite directions, the voltage across it swings twice as far. So the victim's driver must supply about twice the charge.

Spacing reduces coupling to the neighbours but costs tracks, and the gain falls off as the gap grows. A shield is a grounded or supply wire running alongside. It replaces a switching neighbour with a quiet one. So the coupling becomes a fixed load that adds delay but no noise. Clocks often get both through a non-default routing rule; ordinary signals usually just get spacing or a stronger driver.

Run SI-aware timing on the extracted, routed design, with coupling kept in the parasitics. Use timing windows so only aggressors that can switch together count. Check noise glitches against receiver margins on latches, clock pins and asynchronous inputs separately from delay. Fix with spacing, shielding or driver changes, re-extract and re-check, and state which corners and activity assumptions the result covers.

The bigger buffer drives its 17 loads faster, so the shortest path got shorter. The capture clock is still seven buffers late. Hold lost what setup gained. Fix hold by adding delay on the short path near the capture flop, or by reducing the skew. Never fix it by touching the period. Here a smaller buf_2 meets both checks, so pick the smallest drive that closes setup rather than the biggest.

Hold slack depends on the real launch and capture latencies, and before CTS the clock is ideal, with zero skew. Repairing earlier would add delay for skew that may never appear and miss the skew that does. In lesson L5.5 no endpoint failed hold with ideal clocks, while 45 failed after CTS.

A delay cell is built to be slow. In sky130, dlygate4sd3_1 gives about 0.53 ns for 10 µm², while buf_1 gives about 0.08 ns for 3.75 µm². So one delay cell replaces several buffers at far less area per nanosecond. Buffers suit small fixes and are easier to resize later.

Repair against all required corners at once. Then the tool sees the setup cost at the slow corner when it inserts delay at the fast one. Prefer delay on paths with setup slack to spare at every corner. Fix shared skew in the clock tree before adding cells. A repair that must break setup to fix hold shows the constraints or the clock tree need work, not more cells.

The shared net also feeds long paths, and they slow down by the same delay. With tight setup at the slow corner, those paths now fail. Put the delay near each failing D pin instead, where only the short path passes. Then check setup at every corner again.

During manufacturing, metal is built up layer by layer. A long piece of metal connected only to a transistor gate collects charge during etching. That charge can damage the thin gate oxide. The antenna rule limits the ratio of that collecting metal area to the gate area it connects to. Fixes are a diode that gives the charge a safe path, or shorter routing. A jump to an upper layer also works, because the long segment then connects late.

The long lower-layer segment is split, and the parts are joined only when the upper layer is built. By then the path to a driving cell's diffusion exists. So the charge collected on each lower piece is limited to the short segment still attached to the gate.

A diode works whatever the routing, but it is a cell that needs a placement site and adds capacitance to the net. A layer jump costs no cell, only vias and upper-layer tracks, and is done by the router. Lesson L6.6 measures the cost of each on real nets; the lesson's problem asks for protection with fewer diodes.

Every check, run on one final netlist and layout. That means timing in all modes and corners, and IR, EM, DRC, LVS, antenna and equivalence. Each comes with its inputs, tool versions and pass criteria. Anything not run or waived is listed as open with an owner. A later change of geometry or logic invalidates the results it touches, so they are re-run, not carried over.

List it as open, with an owner, a date and the risk it carries. The clean reports beside it do not cover it. If the team accepts the risk, record who accepted it and why, so the tape-out record shows it. Never mark an unrun check as passed.

DRC checks geometry against the foundry's rule deck: widths, spacings, enclosures and densities. It has no idea what the circuit is meant to do. LVS extracts the devices and connections from the layout and compares them with the reference netlist. Two wires shorted by a legal-looking strap pass DRC and fail LVS. A perfectly connected layout with a spacing error passes LVS and fails DRC.

The logic netlist usually has no power pins and no physical-only cells such as taps, fillers and decaps. The layout has all of them. LVS needs a reference built with the same conventions: supplies connected, physical cells either included or excluded by a documented rule. A mismatch there is a reference problem, not a layout bug.

DRC asks whether the shapes can be manufactured. LVS asks whether the shapes form the netlist you meant. Logic equivalence asks whether that netlist computes the same function as the RTL. STA asks whether it does so fast enough at every corner. A clean report in one says nothing about the other three.

Then nothing ties the shipped layout to the RTL. LVS shows that the layout matches the post-ECO netlist. But that netlist was never compared with the RTL. Rerun equivalence on the final netlist, because every check must use the same final data.

Start with constraints that are complete and agreed, and a floorplan that serves the critical data flow. Both are cheap to change only early. Re-time every stage against the same mode and corner set. Keep margins explicit for what later stages add: wire, clock tree, coupling, variation. Close design rules before timing and hold after CTS across all corners. Plan a sign-off review with every check, its inputs and its open items, plus a budget of ECO cycles before the freeze.

Each stage replaces an estimate with a real model. Placement adds estimated wire, and CTS replaces the ideal clock with real latencies and slews. Routing replaces estimated wire with detoured, coupled wire. In lesson L1.1 the same path lost about 0.31 ns from global routing alone. So the target at each stage must leave room for what comes next.

A flat derate applies the same percentage to every cell. That is pessimistic on deep paths, where random variation partly cancels, and can be optimistic on short ones. Depth- and distance-aware tables scale the derate with the number of stages and the spread of the path. Statistical models carry a sigma per cell arc and combine them along the path. All of them need data from the library; the method is only as good as that data.

Stop spending flow iterations on it. Take it to the RTL owner with the evidence: the path, its logic depth and the best slack each fix reached. The structural options are pipelining, retiming, or restructuring the logic, each with a cost in latency or verification. Agree on it early, because an RTL change late in the schedule restarts synthesis, equivalence and the flow.

Pipelining adds a register stage, so latency grows by a cycle. Every interface, model and test that counts cycles must change. Retiming moves existing registers and keeps the latency at the ports. But the internal flops no longer match the RTL, so equivalence needs a sequential check.

Write down the intended behaviour and the physical changes you will allow before touching the layout. Make the timing fix with local resizing or buffering. Make the logic fix with spare cells or minimal new ones. Then legalize, route incrementally and measure every changed cell and connection. Prove the logic fix by equivalence against the corrected RTL. Refresh timing at every corner, plus DRC, LVS and antenna, on the result.

The edited netlist no longer comes from synthesis, so nothing ties it to the RTL except the check. Equivalence against the corrected RTL shows the whole function now matches, not just the failing case. In lesson L7.5 the corrected netlist was proven against corrected RTL. The original netlist was not, and the lesson records it as unproven.

Spare cells are already placed. So a fix that only rewires them can be done in the metal layers, which limits the change. New cells give exactly the gates you need but must be placed, which can move neighbours and touch the base layers. Lesson L7.5's problem asks for a reconnection without new base cells for that reason.

A strong answer gives the block's size, frequency, corners and constraints. Then it gives the floorplan choices with their reasons: utilization, macros, pins and grid. It tells one hard problem in detail, with the numbers before and after and what was tried that did not work. It ends with the sign-off evidence: every check, the corners covered, the open items and who accepted them.

A good story names the change, such as an upsize, a density change or a constraint edit. It gives the metric the change was meant to improve and the side effect: hold, congestion or another corner. It shows how the problem was caught, ideally by a check that ran after every change. It ends with the process fix, such as re-timing all corners after each ECO.