Placement Interview Questions

HPWL is half the perimeter of the bounding box around a net's pins, here 10 + 10 = 20 µm. The shortest rectilinear tree that joins four corners must run three sides of the square, 30 µm. HPWL is exact for two- and three-pin nets without obstacles, and a lower bound for larger nets. That is why placers use it as a fast estimate, not as the routed length.

Any tree that reaches every pin must span the bounding box once horizontally and once vertically. So it is at least the half perimeter. With three pins one trunk and one branch always achieve that. With more pins the tree needs extra branches inside the box, as the four-corner square shows, so real wire exceeds the bound.

HPWL sums pin boxes and ignores how crowded the routing is. The router has to share tracks, so in a dense cluster it detours and uses more wire. In lesson L4.2 raising the target density from 0.6 to 0.95 cut HPWL from about 6244 to 5119 µm while routed wire rose from 18326 to 18719 µm.

Every connected cell would pile into one spot, which is short wire and impossible to build. An analytic placer minimises a smooth wirelength plus a density penalty whose weight grows each iteration. It stops when overflow falls low enough. Overflow is the share of cell area above the target density. In lesson L4.1 the run stopped at iteration 361 with overflow 0.099.

Target density is the local fill the placer aims for; it must sit above the overall utilization or cells cannot spread. A higher target clusters connected cells, which shortens wires but concentrates routing demand on the clusters. Congestion is that demand compared with the tracks available in each routing tile. So the global router's overflow map, not HPWL, says whether the density choice was too aggressive.

Utilization is one number for the whole core: cell area over core area, fixed by the floorplan. Target density is a local goal the placer pushes every region toward, so it controls how tightly cells cluster within that core. A 40 % core can be placed at density 0.6 or 0.95, with very different wire and congestion.

The platform reduces each layer's capacity, by 20 % on sky130 here. This leaves room for pin access, vias and detours that the coarse model cannot see. Overflow is measured against that reduced capacity. Changing the adjustment changes the plan's resources, not the physical tracks, so it can hide congestion rather than fix it.

Start cheap and local: lower the target density or turn on routability-driven placement, which inflates cells in crowded regions. Then look at the cause, such as a pin cluster, a wide multiplexer or a macro channel. Fix that cause with a pin plan or floorplan change. Lower utilization is the expensive last resort. Re-check timing after each step, because spreading costs wire.

Routability-driven placement adds room only where the router predicts overflow. Lower utilization grows the whole block, so area and wire grow everywhere. The local fix keeps the dense, short-wired regions that had no problem. So it is the cheaper first step.

A legal placement has every cell on a row, on a site, in the row's orientation or its mirror, and overlapping nothing. Legalization moves each cell from its rough global position to the nearest legal spot, and displacement measures those moves. A large maximum displacement points to an over-full region. The moves cost wirelength and slack, and detailed placement only partly wins them back.

Each cell has VDD along one edge and VSS along the other. Flipping alternate rows puts the same supply on the boundary between two rows, so neighbours share one rail instead of needing two. A cell placed in a row must take that row's orientation, or its mirror image left to right.

Legalization only makes the placement legal, moving cells as little as possible. Detailed placement then improves a legal placement without breaking it, by swapping and shifting neighbours and mirroring cells to shorten nets. In lesson L4.3 it won back about 530 µm of the 1236 µm that legalization had added.

Legalization moves each cell to a nearby free site without looking at timing. In an over-full region a cell on a critical path can move far. The longer wires add delay on that path. Detailed placement and repair then win part of it back.

Filler cells only keep the rails and wells continuous, so they can be taken out where the new cell goes. Remove the fillers around the edit, place and legalize the new cell, route the change, then insert fillers again and re-check. In the pinned flow fillers go in after detailed routing for exactly this reason.

One small driver feeds 52 reset pins plus the wire. So its edge is far slower than the library allows, and its delay is extrapolated. Repair the design rules first: a buffer tree splits the load and stronger drivers sharpen the edge. Reset is not a clock and needs no skew balancing. But its release is still timed by recovery and removal checks. So re-check those after the tree is built.

The Liberty tables stop at the characterised loads and slews, and beyond them the timer extrapolates in a straight line. In lesson L2.2 an inv_1 at 0.25 pF, well past its 0.18 pF limit, still got a printed delay of 0.8558 ns, which nobody measured. The design-rule report is what flags it.

Resizing swaps in a stronger driver, which is cheap and keeps the topology. But it loads the cell in front of it and cannot help a net that is simply too long. Buffering splits the loads into a tree, so each driver sees a manageable load. The cost is extra cells and delay stages. Repair tools try both and use placement to estimate the wires.

Removal is the hold check of a reset release. The release must not come too soon after the clock edge. Otherwise the flop sees reset and clock at nearly the same time. Here the release arrives 0.3259 ns after the edge but the flop needs 0.3364 ns, so it is 10 ps early. Slow the release path slightly, or reduce the skew between the synchroniser and the flop, exactly as for hold.

The buffer tree adds delay and skew on the release path at every flop. Removal may then pass with margin while recovery, the setup-like check, starts to fail. So re-run both checks after every reset repair, at all corners.