Clock Trees Interview Questions

Latency is when the clock edge reaches a flop. It is source latency up to the clock's definition point, plus network latency through the tree. Network latency is also called the insertion delay. Skew is the difference in latency between two flops, capture minus launch. Only local skew enters a slack: skew between flops joined by a timing path. Global skew, the latest minus the earliest sink anywhere, is a tree quality number.

A setup or hold check compares one launch flop with one capture flop along a path. If no path joins two flops, no check ever compares their clocks, so their latency difference never appears in any slack. It can still matter for power and for clock-domain interfaces, but not for these checks.

Large buffers give sharp edges, low insertion delay and low skew. They cost area and clock power, since the clock switches every cycle. In lesson L5.2 the default tree on the MAC had 0.31 ns insertion delay and 0.008 ns skew at 0.257 mW. A clkbuf_1 tree had about 0.73 ns, 0.045 ns and 0.166 mW. Clocks route on upper, low-resistance metal for the same reason.

The flop gets slower and its timing window moves. In the sky130 library, clock-to-Q of dfxtp_1 grows from about 0.27 to 0.52 ns as the clock slew goes from 0.01 to 1.5 ns. The setup and hold times shift too. That is why clock trees keep edges sharp and why a clock slew limit is part of CTS.

Yes: delaying R's clock by 0.4 ns gives stage A 0.4 ns more and takes 0.4 ns from the stage after R, so both pass. The limit is hold into R, which loses the same 0.4 ns; at 0.6 ns stage A gains more but hold into R fails. Around any loop of registers the skews sum to zero. The delay must later be built from real clock cells, in steps.

Each register's latency is added to the stage it captures and subtracted from the stage it launches. Walk around a loop and every latency appears once with each sign, so the total time available to the loop is unchanged. The best you can do is share it evenly, so the period is bounded by the loop's average stage delay.

Useful skew moves the clock edge and leaves the logic alone. So it costs clock cells and hold margin, and it is invisible to the RTL. Retiming moves gates across the register, which changes the state encoding and needs equivalence checking and sometimes reset changes. Skew is the late, physical fix. Retiming or pipelining is the structural fix when a stage is too long for any clock trick.

Two clkdlybuf4s18_1 cells, the only option that passes both checks. Real cells come in steps, so the built latency rarely matches the SDC number. The window between hold into R and setup of stage A decides which steps are usable. The branch to R is also not shared with the other flops, so its variation is not cancelled by reconvergence pessimism removal.

CPPR credits only the clock segment that launch and capture share, because one wire cannot be early and late at once. The delay cells sit on the branch to R alone. So the tool still derates them late for one side and early for the other. That variation shrinks the usable window.

Making the clock real adds about 0.31 ns of insertion delay to every flop. Internal paths see it at launch and capture, so it cancels. But an input is referenced to the clock at the port, with no tree in front of it. So the capture flop's clock arrives 0.31 ns later relative to the data, and hold loses that much. Outputs lose setup the same way. Model the agreed external clock, for example with source latency on a virtual clock, instead of fixing it with delay cells.

The launch and capture flops both sit behind the same tree. So both edges move later by nearly the same amount. The difference, the local skew, stays small. What changed slightly was skew and the slew-dependent clock-to-Q, 0.1639 to 0.1356 ns in the lesson. Paths that start or end at a port have no tree on the far side, so for them nothing cancels.

A virtual clock has no source pin in the block; it stands for the clock at the external device. Referenced to the real clock, I/O paths shift when CTS makes that clock propagated, by about the insertion delay. A virtual clock with an agreed source latency keeps the external timing fixed. So the I/O budget means the same before and after CTS.

After CTS the capture flop sees the clock later, by the insertion delay. The input delay is still counted from the edge at the clock port. So the data has extra time for setup, and hold gets harder by about the same amount. Outputs move the other way.

Agree one clock model per interface: where each block's clock is assumed to arrive, written as source latency on a virtual clock. Feed the parent's real insertion delays back as they become known. Hold margins stay explicit and owned. Blocks then repair only real short paths, and the top level checks the same interfaces with the real trees.

The gate near the root. Its clock pin sees the clock early, while the enable is launched by a flop deep in the tree. So the enable path faces negative skew and must still meet the gate's own setup check. In lesson L5.6 the root gate failed by 0.1466 ns and the leaf gate passed with 0.0715 ns. A gate near the root saves more clock power, so the choice is power against enable timing.

A setup and a hold check on the enable against the gate's clock, like a flop's data pin. The enable must settle before the clock rises, so the latch inside captures it cleanly. It must not change too soon after. In the sky130 cell the enable setup time ranges from about 0.04 to 0.32 ns depending on the slews.

If the enable changes while the clock is high, the AND output pulses or cuts the high phase short. Flops may count that glitch as a clock edge. The integrated cell latches the enable while the clock is low. So the enable can only change the output during the low phase. The RTL track's lesson R2.3 shows the glitch in simulation.

The mux keeps the clock running and selects the old value when the enable is low. The flops and the clock tree still burn power every cycle, and each flop gains a mux. Clock gating stops the clock to the whole bank with one cell. That saves power but puts a timed enable into the clock tree. In lesson L5.6 the mux path also failed setup, by 0.1325 ns, because the enable arrives late.

CTS builds the tree on the gated clock after the gate, so the gate's delay adds to every gated flop's latency. In lesson L5.6 the gated MAC's latency was about 0.47 ns against about 0.31 ns ungated. Paths between gated and ungated flops then see that difference as skew and must meet setup and hold.