Floorplanning Interview Questions

Utilization is total cell area divided by core area. So the floorplan divides the cell area by the target to get the core. Then it snaps the core to whole rows and sites. A fuller core gives shorter wires and a smaller die. But it leaves less room for routing and for the buffers, clock cells and fixes added later. In lesson L3.1, a 70 % target became 73 % after taps and 77 % after CTS.

Standard cells sit in rows of a fixed height and on sites of a fixed width, 2.72 by 0.46 µm for sky130 high density. The core must hold a whole number of rows and sites, so its corners snap to that grid. The log prints a message when it does. That is also why the effective utilization differs a little from the target.

Nets get stretched along the long side, so wirelength grows, and the short edges have less room for pins. In lesson L3.1 the same FIFO at 70 % went from 32 rows of 193 sites to 65 rows of 96 sites. Placed wirelength rose from about 6807 to 7207 µm. Pick the aspect ratio from the pin and macro plan, not by default.

Utilization is one number for the whole core: cell area over core area, fixed by the floorplan. Target density is a local goal the placer pushes every region toward, so it controls how tightly cells cluster within that core. A 40 % core can be placed at density 0.6 or 0.95, with very different wire and congestion.

The core is 28.52 µm wide. But one pair of met4 straps needs a 13.6 µm offset plus 15.2 µm of strap width, about 28.7 µm. So the grid cannot fit even once. Widen the core by lowering utilization or changing the aspect ratio. Or use a grid definition with narrower straps or a smaller offset for small blocks. The grid is part of the floorplan, not something added after it.

The cells' own rails on met1 run along every row edge, shared between flipped neighbouring rows. Vertical met4 straps and horizontal met5 straps, alternating VDD and VSS about 27 µm apart per net, carry current across the block. Via stacks join them where same-net straps cross. Upper metals are thicker and less resistive, so the bulk current runs high.

Halving the pitch cuts IR drop and costs routing tracks; doubling it frees tracks and raises the drop. Lesson L3.5 used a 3324-cell block. There the worst drop went from 0.00148 V to 0.00069 V with half the pitch, and to 0.00332 V with double. The met4 routing resources moved from 9268 to 7880 and 9924. Measure both sides before you choose.

Between two straps, a rail with uniform load drops most at the middle, by j·r·D²/8. So that part grows with the square of the spacing D. The measured worst drop went from 0.00148 V to 0.00332 V, about 2.2 times. The rail part is only one share of the total, so the growth is less than four times.

The n-wells and p-substrate under the cells are no longer tied to their supplies, which invites latch-up. The sky130 high-density cells have no taps inside them, so tap cells must be placed in every row. Here they sit in a checkerboard about every 14 µm. The rule comes from the process; the lesson found no public numeric tap distance to check against.

Place macros first, usually against the core edges, with their pins facing the logic they talk to. Keep a halo (a keep-out ring with no standard cells) around them. Size the channel from the nets that must cross it. Tracks are the channel width over the layer pitch, less obstructions and power. In lesson L3.3 a 9 µm channel overflowed by 522 routing resources. A 37 µm channel, or turning the pins to the top, gave zero overflow.

Divide the width by each layer's pitch: met2 at 0.46 µm gives about 19 tracks and met4 at 0.92 µm about 9. Then subtract what is already used, such as power straps and pin access, and keep the router's reserve. That is far fewer than the nets two 39-pin macros want to exchange.

A halo is a keep-out ring attached to the macro, so it moves with the macro. It keeps standard cells off the macro's edges and pin access. A blockage is a region you draw on the floorplan to keep cells, or routes, out of an area. It can be for any reason, such as a channel you want left for wires. Both cost placement area, so size them from the routing they protect.

Change where the nets go instead of where the channel is. In lesson L3.3, moving the macros' pins to the top edge sent the crossing nets out of the channel. Overflow fell to zero with a 4.6 µm halo, and wirelength dropped from 4981 to 3774 µm. Pin moves on a hard macro are an agreement with its owner, so raise them early.

Overflow concentrated in one place, with low usage overall, points to a local cause. Here that cause is the channel, not a block that is too full. Look at where the demand comes from. It may be nets crossing the channel, pin access at the macro edges, or straps that took the tracks. The fixes act on that cause: a wider channel, pins turned away from it, or a different halo (keep-out ring). Each fix is measured by routed wirelength and timing, not by overflow alone.

Global routing plans each net through coarse tiles and counts tracks per tile edge. That says nothing about how a wire reaches a pin or which vias fit. Detailed routing picks real tracks, vias and pin access under width, spacing, area and enclosure rules. It can run out of iterations and leave violations in a readable layout, so its own count matters too.

Not necessarily. The router checks the rules it knows from the technology LEF, a subset of the foundry deck. Full DRC on the merged layout, with cells, fill and every rule, is a separate run. Antenna checking is separate again. Sign-off quotes which checker ran with which deck.

Density and routability-driven placement spread cells. That helps when demand comes from local crowding. It does nothing for nets that must cross a fixed gap. Floorplan fixes, such as macro position, channel width or pin edges, change where the nets go. Density changes distances but not the netlist's connectivity, so a connectivity hot spot needs the floorplan answer.

Start cheap and local: lower the target density or turn on routability-driven placement, which inflates cells in crowded regions. Then look at the cause, such as a pin cluster, a wide multiplexer or a macro channel. Fix that cause with a pin plan or floorplan change. Lower utilization is the expensive last resort. Re-check timing after each step, because spreading costs wire.

Routability-driven placement adds room only where the router predicts overflow. Lower utilization grows the whole block, so area and wire grow everywhere. The local fix keeps the dense, short-wired regions that had no problem. So it is the cheaper first step.

IR drop is supply voltage lost across the grid's resistance. So cells far from the straps see less than the nominal supply and slow down. Electromigration is metal wearing out under high current density and temperature. The technology limits it as current per micron of wire width and per via. A denser grid and wider straps lower both, at the cost of routing tracks.

Doubling the spacing doubles two things. It doubles the current the middle of the rail must carry, since twice as many cells feed through it. It also doubles the resistance that current flows through. With uniform load and both ends held at the supply, the peak drop is j·r·D²/8. Lesson L3.5 checks that model against a measured rail and finds it close.

Static analysis applies each cell's average current from power analysis and solves the grid once, which finds weak straps and long rails. Dynamic analysis follows current over time. So it sees many cells switching together after a clock edge, and the local droop that decaps must cover. A block can pass static analysis and still fail dynamic, so sign-off states which one ran and with what activity.

It makes every cell 5 % slower everywhere on the late paths, whatever the drop at that cell actually is. It is easy to run and says nothing about where the grid is weak or how this library's delay changes with voltage. On the lesson's path it moved the slack from 0.1462 to 0.1291 ns, a number with no physical basis.

The placer pulls cells toward the pins they connect to. So a poor pin plan drags whole cones of logic toward one edge. It also stretches the internal nets between them. In lesson L3.2, putting all 39 pins on the left edge raised placed wirelength from about 6041 to 7365 µm. The I/O nets were only part of it. Pin edges are also an agreement with the top level, so plan them early.

A pin is reached by a wire running into the edge. So it uses a layer whose preferred direction points into that edge. Layer met3 runs horizontally, which suits the left and right edges, and met2 runs vertically, which suits the top and bottom. A pin on the wrong layer forces a wire against its preferred direction, which blocks tracks.

For the lesson's MAC, inputs on the bottom and outputs on the top gave about 6853 µm of placed wire. The flow's plan gave 6041 µm. The flow spreads each pin near the cells that use it. A data-flow plan is still often the right call when the top level needs it. The point is to measure the cost of the plan the parent wants rather than guess it.

Re-run placement with the new pin plan. Compare wirelength, congestion near the new edge and the timing of the paths through the bus. The cells that talk to the bus will migrate, so internal paths can move too, not only the I/O nets. Agree only with the measured cost in hand, and update the I/O budgets with the parent, because the boundary delays change.

Then the boundary paths are signed off against delays that no longer exist. The new edge changes the wire length on both sides of the pin. Re-derive the input and output delays with the parent, from the new floorplan. Until then, list the I/O paths as open.