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Interview Question · Code Writing

Beat Addresses for FIXED, INCR and WRAP

L0 FresherL1 Junioraxibursts

The Question

The interviewer asks

Write the function that returns the address of beat n of an AXI burst, for all three burst types. Then give me the addresses of a 4-beat, 4-byte WRAP burst starting at 0x38.

Reveal the Model Answer

Beat 0 is always the start address, and FIXED repeats it. INCR adds n times the size to the start aligned down to the size. WRAP does the same inside a window of size times length bytes, aligned to that total. It returns to the window's base when it reaches the top. So WRAP4 of 4 bytes at 0x38 has window 0x30 to 0x3F and visits 0x38, 0x3C, 0x30, 0x34.

A Four-Beat WRAP Write at 0x108 Lands in MemoryMeasured: cycle 0 is edge 3, where the request is taken. The beat address is the one the task drives; the row it lights is where the memory puts the bytes.
AWWBManagerWRAP, 4 beats of 4Memory 0x100 to 0x10flane01230x1000x1040x1080x10c

Each cell is one byte; lane 0 is the lowest address of its row. The pill carries the beat address.

01234567clkawvalidawaddr108xwvalidwreadybeat_addrx10810c100104wstrb00001111xwlastbvalid
  1. Cycle 0

    The request: start 0x108, four beats of four bytes, WRAP. The window is 16 bytes from 0x100, because 0x108 rounded down to 16 is 0x100.

  2. Cycle 1

    Beat 0 lands at the start address, row 0x108.

  3. Cycle 2

    Beat 1 at 0x10c: start plus one size, still inside the window.

  4. Cycle 3

    The next address would be 0x110, the end of the window. Beat 2 wraps to 0x100.

  5. Cycle 4

    Beat 3 at 0x104, with wlast. Four rows lit, the whole 16-byte line, in the order 0x108, 0x10c, 0x100, 0x104.

  6. Cycle 7

    The response. The dump reads a2 a3 a0 a1 from 0x100: the data of beats 2 and 3 sits below the data of beats 0 and 1.

Measured: a WRAP4 of 4-byte beats at 0x108. The window is 0x100 to 0x10F, so the beats go 0x108, 0x10C, 0x100, 0x104.

RUNIcarus Verilog · in your browser
Edit the code, then run it
Expected: INCR start 00001000: 00001000 00001004 00001008 0000100c INCR start 00001002: 00001002 00001004 00001008 0000100c WRAP start 00000038: 00000038 0000003c 00000030 00000034 WRAP start 00000034: 00000034 00000038 0000003c 00000020 00000024 00000028 0000002c 00000030 FIXED start 00000040: 00000040 00000040 00000040 00000040

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Fresher)

A good fresher answer gets INCR and FIXED right. It also gets the WRAP example right: 0x38, 0x3C, 0x30, 0x34.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak It

  1. Beat Addresses for FIXED, INCR and WRAP
  2. WhyWhy WRAP Bursts ExistL1 Junior

    Who actually issues WRAP bursts, and why not just use INCR?

    Reveal the Model Answer

    Caches issue them: on a miss, the CPU wants the word it stalled on first (critical word first). But the cache still needs the whole line. A WRAP burst starts at the missing word and wraps around the line-aligned window. So the line is filled in one transaction that never leaves it. INCR from the missing word would run past the end of the line.

    Self-Check

    Tick each key point you covered in your answer.

  3. What IfIllegal WRAP BurstsL1 JuniorL2 Mid-Level

    A manager issues a WRAP burst of 3 beats, and another at 0x102 with 4-byte beats. What does your checker say?

    Reveal the Model Answer

    Both are illegal. A WRAP burst must be 2, 4, 8 or 16 beats long, so length 3 fails. It must also start aligned to its transfer size, so 0x102 with 4-byte beats fails. A checker flags both at the request handshake, before any data moves. FIXED is limited to 16 beats, and INCR may run to 256.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer gives both WRAP rules. The length must be 2, 4, 8 or 16, and the start must be aligned to the size.

  4. WhyWhere a WRAP Burst WrapsL1 JuniorL2 Mid-Level

    Why must a WRAP burst start aligned and have 2, 4, 8 or 16 beats? Where does it wrap?

    Reveal the Model Answer

    The burst lives in a window of beats times bytes per beat, aligned to that size. The lowest address of the window is the wrap boundary. With a power-of-two length, hardware finds the window by masking low address bits. An aligned start keeps every beat a whole transfer inside it.

    Self-Check

    Tick each key point you covered in your answer.

    Spec Misquote

    "The wrap window starts at the burst's start address."

    It starts at the start address aligned down to the total size. A burst that starts mid-window wraps back below its start.

    Source AMBA AXI Protocol Specification IHI 0022L §A3.1.4 Burst attribute

  5. Break ItThe WRAP Formula at the Top of MemoryL2 Mid-LevelL3 Senior

    Your beat-address model wraps with if (a >= boundary + window) a -= window. It passes every regression. Where does it break?

    systemverilog
    // All arithmetic here uses the address width.
    a = a + bytes_per_beat;
    if (a >= boundary + window) a -= window;
    Reveal the Model Answer

    At the top of the address space. With 32-bit unsigned arithmetic, a window that ends at 2^32 makes boundary + window overflow to 0. So the test is always true, and beat 1 is pulled down a whole window. Comparing the offset, a - boundary >= window, never overflows. The twin runs both forms at 0x108 and at 0xFFFFFFF8: they agree in the middle and disagree at the top.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer finds the overflow once it sees the address near the top of memory.

    Missed Corner

    "The formula matches the spec equation, so it is right everywhere."

    The spec equation uses unbounded integers. A 32-bit model of it overflows in the last window of the space. Regressions that never reach that window never see the bug.

    Run It

    The sum form passes in the middle of memory and fails in the last 16 bytes of the 32-bit space. The offset form passes both.

    RUNIcarus Verilog · in your browser
    Edit the code, then run it
    Expected: PASS WRAP4x4 at 00000108: 00000108 0000010c 00000100 00000104 FAIL WRAP4x4 at fffffff8: fffffff8 ffffffec fffffff0 fffffff4 (beat 1 should be fffffffc)
    See the Fix
    module tb;
      localparam bit BUGGY = 0;   // 1: wrap test written as a >= boundary + window
      // Beat n of a WRAP burst of len beats of nb bytes (32-bit addresses).
      function automatic int unsigned beat(int unsigned start, int len, int nb, int n);
        int unsigned window = nb * len, lo = (start / window) * window, a;
        if (n == 0) return start;
        a = (start / nb) * nb + n * nb;
        if (BUGGY ? (a >= lo + window) : (a - lo >= window)) a = a - window;
        return a;
      endfunction
      // Compare beats 0-3 of a WRAP4 x 4-byte burst with the addresses the spec equations give.
      task automatic check(int unsigned start, int unsigned e0, e1, e2, e3);
        int unsigned want[4];
        string s = "";
        int bad = -1;
        want[0] = e0; want[1] = e1; want[2] = e2; want[3] = e3;
        for (int n = 0; n < 4; n++) begin
          s = {s, $sformatf(" %h", beat(start, 4, 4, n))};
          if (bad < 0 && beat(start, 4, 4, n) != want[n]) bad = n;
        end
        if (bad < 0) $display("PASS WRAP4x4 at %h:%s", start, s);
        else $display("FAIL WRAP4x4 at %h:%s (beat %0d should be %h)", start, s, bad, want[bad]);
      endtask
      initial begin
        check(32'h0000_0108, 32'h0000_0108, 32'h0000_010c, 32'h0000_0100, 32'h0000_0104);
        check(32'hffff_fff8, 32'hffff_fff8, 32'hffff_fffc, 32'hffff_fff0, 32'hffff_fff4);  // the last 16 bytes
        $finish;
      end
    endmodule

    Prints: PASS WRAP4x4 at 00000108: 00000108 0000010c 00000100 00000104 PASS WRAP4x4 at fffffff8: fffffff8 fffffffc fffffff0 fffffff4

  6. Prove ItSolve P2.6.1: The Address of Every BeatSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P2.6.1

  7. Prove ItSolve P2.6.2: The WRAP BoundarySimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P2.6.2

What People Get Wrong

Common wrong answers and why they fail.

Missed Corner

"Every beat is start + n × size."

It is wrong for an unaligned start, because beats after the first are aligned. 0x1002 + 4 = 0x1006, but beat 1 is at 0x1004. The run shows it.

Source AMBA AXI Protocol Specification IHI 0022L §A3.1.6 Transaction equations

Spec Misquote

"The wrap boundary is the start address aligned to the transfer size."

It is aligned to the whole burst, size times length. Aligning to the size would make a WRAP burst never wrap.

Source AMBA AXI Protocol Specification IHI 0022L §A3.1.4 Burst attribute; §A3.1.6 Transaction equations

Learn It, Then Prove It