Interview Question · Concept
Outstanding Transactions and Bandwidth
- Asked at Qualcomm
The Question
The interviewer asks
A memory answers every single-beat read 8 cycles after accepting it. How many reads must a manager keep outstanding to use the read data channel fully?
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Reveal the Model Answer
About latency times rate: 8 cycles times one read per cycle, so 8 in flight. Throughput is outstanding transactions (issued but not yet answered) divided by latency, which is Little's law. So one read at a time gives one beat every 8 cycles. The run shows 32 reads taking 257 cycles with a window of 1, 68 with 4 and 40 with 8. A window of 16 is no faster, because then the clock is the limit.
A request token flies out, a response token flies back; the lit slot is the request in flight.
- Cycle 1
Request 0 is taken. The target now holds one request in flight.
- Cycle 2
The initiator waits. With a window of one, nothing else may start.
- Cycle 4
Response 0 arrives, three cycles after the request. Only now can request 1 start.
- Cycle 5
Request 1 is taken, four cycles after request 0.
- Cycle 12
Response 2 at cycle 12. Three transactions in twelve cycles: one response every four cycles.
Three of every four cycles carry nothing. The link is idle while the initiator waits for a response it has already asked for.
Requests leave every cycle; the lit slots are the requests in flight; responses return in the same order.
- Cycle 1
Request 0 is taken, exactly as before.
- Cycle 2
Request 1 is taken one cycle later. The initiator did not wait for response 0.
- Cycle 3
Three requests in flight. The target answers each one three cycles after taking it.
- Cycle 4
Response 0 at cycle 4: the same latency as the serial run.
- Cycle 6
Response 2 at cycle 6. Three transactions in six cycles instead of twelve. The throughput doubled; the latency did not move.
Pipelining never shortens a transaction. It fills the cycles between them.
window 1: 32 reads in 257 cycles, 12% of the data channel window 2: 32 reads in 130 cycles, 24% of the data channel window 4: 32 reads in 68 cycles, 47% of the data channel window 8: 32 reads in 40 cycles, 80% of the data channel window 9: 32 reads in 40 cycles, 80% of the data channel window 16: 32 reads in 40 cycles, 80% of the data channelSelf-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says more transactions in flight hide the latency, while the latency itself stays the same.
What Interviewers Listen For (Mid-Level)
A good mid-level answer works out the needed window from latency and rate. It knows the subordinate's acceptance limit caps it.
What Interviewers Listen For (Senior)
A good senior answer sizes the manager's read-data buffer to the window. It knows a manager must accept all the read data it asked for.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
What IfProve ItBreak ItCompareScale It
- Outstanding Transactions and Bandwidth
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CompareREADY High in AdvanceL1 JuniorL2 Mid-Level
A subordinate raises ARREADY only after it sees ARVALID. Legal? What does it cost?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Legal: READY may wait for VALID. But with a registered READY (driven from a flip-flop), it costs a cycle on every request. The handshake cannot happen in the cycle VALID first appears. The spec recommends READY high by default on request channels; the subordinate must then be able to accept any request presented. Lesson P2.5 measured RREADY-after-RVALID stretching four read beats from edges 14-17 to 21, 23, 25, 27.
Self-Check
Tick each key point you covered in your answer.
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What IfWhat a Register Slice CostsL2 Mid-Level
Timing fails on a long AXI path, so you add register slices. What do they cost in latency and in bandwidth?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Each stage adds a cycle of latency in its direction. It costs no bandwidth if the slice sustains one beat per cycle. The manager must then keep enough transactions outstanding to cover the longer round trip. VALID must go through as many stages as its payload, but different channels may get different numbers of stages. Lesson P2.5 measured two stages moving a write response from edge 10 to 14.
Self-Check
Tick each key point you covered in your answer.
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Break ItA Register Slice That Drops a BeatL2 Mid-LevelL3 Senior
Break it: a slice registers READY to cut the timing path, but it has only one data register. What happens at the first stall?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
With READY from a flop, the sender sees the stall one edge late. So one extra beat is accepted on that edge. With only one register, that beat overwrites the held beat, and data is lost. A real slice adds a skid register, so it holds two beats and still passes one per cycle.
Self-Check
Tick each key point you covered in your answer.
Misconception
"A registered READY is just a slower READY; nothing is lost."
The sender sees READY one edge late and sends one more beat. Without room for it, that beat overwrites the held one.
Source Lesson R4.4 key points
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Scale ItSizing a DMA's Outstanding CapabilityL3 Senior
A DMA on a 128-bit AXI port reads from DDR with a loaded latency around 200 cycles. How do you size its outstanding reads and its buffers?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Cover latency times rate: about 200 beats in flight at one beat per cycle. With 16-beat bursts, that is about 13 outstanding reads, rounded up for latency spread. The manager must be able to accept all data it requested. So it needs about 200 × 16 bytes of read buffering, or a sink that always accepts data. Then check what the interconnect and memory controller actually accept; their limits, not the DMA's, often set the ceiling.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer does the latency times bandwidth arithmetic. It sizes the data buffer from the rule that a manager accepts all data it asked for. It checks the limits downstream and how IDs are used.
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Prove ItSolve P2.5.1: An Issuer with N OutstandingSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"Pipelining reduces the latency of each read."
Each read still takes 8 cycles from request to data. Pipelining overlaps reads, so the idle cycles between them vanish. Throughput rises; latency does not.
Source Lesson P2.5, measured on Icarus Verilog 12
Half-Truth
"Just make the window as large as possible."
Past latency times rate it buys nothing: windows 9 and 16 equal 8 in the run. It also costs tracking state and read-data buffering.
Source AMBA AXI Protocol Specification IHI 0022L §A2.6 AXI transactions and transfers