Interview Question · Concept
Write Data Before the Write Address
The Question
The interviewer asks
Can write data arrive at a subordinate before its write address? And when may the subordinate raise BVALID?
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Reveal the Model Answer
Yes. The protocol sets no order between AW and W, so data may come before, with or after its address. The subordinate may wait for either or both VALIDs before raising either READY. But the manager must never wait for a READY before raising AWVALID or WVALID. BVALID may rise only after both the address and the last data beat (WLAST) have been accepted. It must not wait for BREADY.
Both blocks wait. Neither wire lights, so no address ever moves.
- Cycle 0
The engine has an address to send. It will raise
AWVALIDas soon as it seesAWREADY. - Cycle 1
The port has four free request slots. It will raise
AWREADYas soon as it seesAWVALID. - Cycle 4
Four edges later nothing has changed, and nothing ever will. The protocol settles who moves first; the engine broke that rule.
Neither wire ever rises. A subordinate may wait for VALID, so the manager broke the rule by waiting for READY.
Manager
Raises
AWVALIDandWVALIDwithout waiting forAWREADYorWREADY, for every beat.Subordinate READYs
May wait for
AWVALID,WVALIDor both beforeAWREADYorWREADY, or raise them early.Subordinate B
Raises
BVALIDonly after the AW handshake and the W handshake of the beat withWLAST, and never waits forBREADY.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer states the three rules between AW, W and B. It says W data may arrive before its AW address.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains the deadlock pair. The manager holds W until it sees AWREADY, and a legal subordinate holds AWREADY until it sees WVALID.
What Interviewers Listen For (Senior)
A good senior answer knows an interconnect must hold early write data until the address is decoded. So W-before-AW traffic is a standard stress test.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItScale It
- Write Data Before the Write Address
-
WhyWhy VALID Must Not Wait for READYL1 Junior
Why is it the sender that is forbidden to wait, and not the receiver?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Someone has to move first, or two polite blocks wait forever. The spec picks the sender: VALID may never wait for READY. READY may wait for VALID, or be high early. So every handshake makes progress as long as the sender has something to send. Receivers can also save power or logic by raising READY only on demand.
Self-Check
Tick each key point you covered in your answer.
-
Break ItCatching a VALID That WaitsL2 Mid-LevelL3 Senior
Your protocol checker binds every AXI rule as an assertion. Will it catch a manager whose WVALID waits for AWREADY?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Not by itself. On the wires, the illegal manager looks legal against a subordinate that raises AWREADY early. Against a subordinate that waits for WVALID, nothing moves, and no safety property fails on a bus where nothing moves. You need a watchdog or liveness check (a VALID is eventually accepted). You also need stimulus that includes a subordinate holding AWREADY until it sees WVALID.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says a timeout or an
s_eventuallyliveness property is needed, because no safety check fails when nothing moves.What Interviewers Listen For (Senior)
A good senior answer adds that the bench must include the subordinate behaviour that triggers the bug. Otherwise even the watchdog never fires. It makes "READY waits for VALID" a coverage item.
-
Scale ItVerifying an AXI InterconnectL3 SeniorL4 Staff
Walk me through how you would verify an AXI interconnect. What checks, what coverage, and which bugs are you most worried about escaping?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Put a protocol checker on every manager and subordinate port. A fabric re-registers what it forwards, so it hides a subordinate's fault from the manager side. Add an end-to-end scoreboard keyed by manager and ID that checks routing, data, ID restore and same-ID order across subordinates. Test every region edge and hole for full-length DECERR. Stress with random back-pressure (READY held low), W before AW, maximum outstanding and racing exclusives, with watchdogs for deadlock.
Bug that escapes What catches it Equal-length same-ID responses swapped scoreboard keyed by ID and address VALID waiting for READY (deadlock) watchdog or liveness property, plus a subordinate that waits for VALID Data in the wrong lanes with legal strobes byte-level data check Subordinate stability bug behind a register slice checker bound at the subordinate port Same-ID requests to two subordinates reordered end-to-end per-ID order check with unequal latencies Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer puts a checker on every port, plus an end-to-end scoreboard keyed by manager and ID, and decode tests.
What Interviewers Listen For (Staff)
A good staff answer explains why each kind of escaped bug needs its own catcher. It turns the plan into sign-off criteria with coverage on ordering and decode.
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What IfEarly Write Data at an InterconnectL2 Mid-Level
Write data reaches an interconnect two cycles before its address. What must the interconnect do with it?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Hold it. The interconnect cannot know which subordinate the data belongs to until it decodes the address. So it must realign data with request, and present WVALID only to the destination. That means buffering W, or holding WREADY low, until the matching AW is decoded, in AW order. AXI4 write data carries no ID, so it follows the address order.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve P2.3.1: The Write DependenciesSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"The manager should send the address first and the data after AWREADY; that is the natural order."
A subordinate is allowed to wait for WVALID before raising AWREADY. Against such a subordinate this manager deadlocks: each side waits for the other. The twin shows no B after 20 cycles, and B after 3 when both VALIDs go up together.
Run It
The subordinate waits for both VALIDs, which is legal. The manager that holds its data until AWREADY never gets a response. The fixed manager raises both VALIDs together.
FAIL manager waits for AWREADY before WVALID: no B after 20 cycles (AWVALID=1 AWREADY=0 WVALID=0)See the Fix
module tb;
localparam bit BUGGY = 0; // 1: the manager holds WVALID until it sees AWREADY
logic clk = 0, rst_n = 0;
always #5 clk = ~clk;
logic awvalid = 0, awready = 0, wvalid = 0, wready = 0, bvalid = 0, bready = 1;
// Subordinate (legal): it may wait for AWVALID and WVALID before raising either READY (A2.3.2).
// It accepts address and data together one cycle after it has seen both, then answers on B.
always @(posedge clk) begin
if (!rst_n) begin awready <= 0; wready <= 0; bvalid <= 0; end
else begin
awready <= awvalid && wvalid && !awready;
wready <= awvalid && wvalid && !wready;
if (awvalid && awready) bvalid <= 1; // one-beat write: address and data move together here
else if (bvalid && bready) bvalid <= 0;
end
end
// The manager issues one single-beat write and gives up after 20 cycles without a response.
task automatic write(bit data_waits_for_awready, string name);
int n = 0;
bit got_b = 0;
rst_n = 0; awvalid = 0; wvalid = 0;
repeat (2) @(posedge clk); #1 rst_n = 1;
awvalid = 1;
if (!data_waits_for_awready) wvalid = 1; // legal: no VALID waits for a READY
while (!got_b && n < 20) begin
@(posedge clk); n++;
if (bvalid && bready) got_b = 1;
if (awvalid && awready) begin // address taken (with the data, for the legal manager)
#1 awvalid = 0;
wvalid = data_waits_for_awready; // the illegal manager would offer its data only now
end
end
if (got_b) $display("PASS %s: B received after %0d cycles", name, n);
else $display("FAIL %s: no B after 20 cycles (AWVALID=%b AWREADY=%b WVALID=%b)", name, awvalid, awready, wvalid);
#1 awvalid = 0; wvalid = 0;
endtask
initial begin
if (BUGGY) write(1, "manager waits for AWREADY before WVALID");
else write(0, "manager drives AWVALID and WVALID together");
$finish;
end
endmodulePrints: PASS manager drives AWVALID and WVALID together: B received after 3 cycles
Spec Misquote
"B can be sent once the last data beat is in, even if the address has not been taken yet."
That was AXI3. From AXI4 the subordinate must also have accepted the address before BVALID.
Source AMBA AXI Protocol Specification IHI 0022L §A2.3.2 Dependencies between channel handshake signals; AMBA AXI and ACE Protocol Specification IHI 0022H.c §A3.3.1