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Interview Question · Concept

Credits Versus Ready

L2 Mid-LevelL3 Seniorhandshakeflow controlcredits

The Question

The interviewer asks

When would you choose credit-based flow control instead of valid/ready, and what does it cost?

Reveal the Model Answer

Choose credits when the answer takes cycles to travel: long wires, many register stages, chip-to-chip links or a network on chip. The receiver hands out one credit per free buffer entry in advance. The sender spends one credit per beat, so no per-cycle ready crosses the link. The cost is buffering. The receiver needs about as many entries as beats sent during a credit's round trip.

Three Credits on a Link with a Two-Cycle ReturnThe source's slots are its credits; the sink's slots are its entries. A credit comes back two cycles after the consumer takes a beat.
datacreditSourcespends creditsSink3 entries

A beat spends a credit from the source; a returned credit lights one again. The sink never sees more beats than it has slots.

0123456789has_beatvaliddataxb0b1b2xb3xb4b5takecredit
  1. Cycle 1

    The source starts with three credits, one per free slot, and spends one per beat.

  2. Cycle 3

    Three beats sent, no credits left. The source stops by itself: nothing asked it to.

  3. Cycle 4

    The credit for b0 arrives, two cycles after the consumer took it.

  4. Cycle 5

    One credit, one beat. The sink cannot overflow: every beat in flight owns a slot.

  5. Cycle 8

    Credits trickle back as the consumer drains. On a longer wire the source would need more of them to keep busy.

The number of credits must cover the round trip: beats sent during the time a credit takes to come back.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Mid-Level)

A good mid-level answer explains that a credit is a free buffer entry granted in advance. It sizes the buffer to cover the round trip of a credit.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

  1. Credits Versus Ready
  2. WhyHow Many CreditsL2 Mid-Level

    The credit return takes 4 cycles end to end. How many credits does the sender need to stream at one beat per cycle?

    Reveal the Model Answer

    At least as many as the beats it can send during one credit's round trip. The round trip is the forward delay, the receiver's turnaround and the return delay. With fewer, the sender stops and waits while the receiver is empty. Measure the real round trip, including every register stage. Rounding it down is the usual mistake.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer sizes the credits to the full round trip, every register stage included. It explains why too few credits leave the receiver empty while the sender waits.

  3. CompareSizing a FIFO with No BackpressureL1 JuniorL2 Mid-Level

    The producer cannot be stalled. The consumer can pause for 20 cycles. How deep must the FIFO be?

    Reveal the Model Answer

    It must fit the beats it already holds when the pause starts, plus every beat that arrives during it. Subtract any beats that leave. With one held and one arriving per cycle for 20 cycles, that is 21 entries. A 16-deep FIFO loses 5. If the producer is faster on average than the consumer, no depth is enough; only flow control fixes that.

    The Same Stall with No Ready WireSame traffic, same 4-entry FIFO, but the link has no ready. A beat that finds the FIFO full is dropped.
    dataouttakedropSourcenever heldFIFO4 entries, no readyConsumerstops for 4 cyclesDroppednobody is told

    A lit wire carries a 1. A pill is a transfer in that cycle; slots are the entries held.

    01234567891011validdataxb0b1b2b3b4b5b6b7xdropout_validout_dataxb0b1b2b3b4b7take
    1. Cycle 3

      The consumer stops and the FIFO fills, as before.

    2. Cycle 6

      Full, and there is no ready to say so. b5 arrives and is thrown away.

    3. Cycle 7

      b6 is lost too: the beat taken at this edge frees room only afterwards.

    4. Cycle 11

      The consumer gets b4 and then b7. Two beats vanished, and no signal recorded it.

    A 4-entry FIFO with no ready wire. Once it is full, each new beat is dropped, and no signal records the loss.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer does the arithmetic correctly: the beats already held plus the beats that arrive during the pause.

  4. Break ItThe Credit That Went MissingL3 Senior

    A credited link slows down after hours of traffic and finally hangs. What would you suspect, and what check finds it on the first lost credit?

    log
    Illustrative credited-link excerpt
    At reset: available credits=8
    After traffic drains: available credits=7
    After another traffic interval drains: available credits=6
    After long operation: available credits=0; sender stalled
    Reveal the Model Answer

    A credit leak: a credit returned during reset, dropped on a flush, or a beat sent without spending one. Each loss quietly shrinks the window until it reaches zero. Check conservation every cycle: sender credits plus beats in flight plus receiver free entries equals the configured total. Also check that the full count is back whenever the link is idle.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer states the rule that the total number of credits never changes. It checks it every cycle and when the link is idle, and adds reset and flush tests.

  5. What IfA Credited Link Reset on One SideL3 Senior

    What if the receiver resets while the sender keeps running?

    Reveal the Model Answer

    The receiver comes back with all its entries free, but the sender still holds its old credits. Those credits are now counted twice, so the sender can overrun the receiver. The spec gives the transmitter no credits and the receiver all of them in reset. So both sides must reset together, or re-start the link from that state.

    Self-Check

    Tick each key point you covered in your answer.

    Missed Corner

    "Each side resets its own counter, so they stay in step."

    They stay in step only if both reset together. A one-sided reset breaks the conservation sum.

    Source AMBA AXI Protocol Specification IHI 0022L §A2.4.1 Credited flow control

  6. Prove ItSolve P1.6.2: A Credit CounterSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P1.6.2

What People Get Wrong

Common wrong answers and why they fail.

Half-Truth

"Credits are always faster than ready."

Too few credits throttle the link, even with an empty sink. Lesson P1.6 measures 25 cycles of waiting for 12 beats, with 2 credits on a 4-cycle return.

Spec Misquote

"The sender starts with all the credits."

In AXI5 credited transport, the transmitter has no credits in reset. The receiver holds them all and hands them out afterwards.

Source AMBA AXI Protocol Specification IHI 0022L §A2.4.1 Credited flow control

Learn It, Then Prove It