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Interview Question · Waveform

The Ninth Clock: ACK and NACK

L0 FresherL1 Juniori2cack
  • Likely at Analog Devices

The interviewer asks

Draw one I2C byte with its acknowledge. Who drives SDA in the ninth clock on a write, and on a read? Why does the controller NACK the last byte it reads?

text
SCL slot:    1 2 3 4 5 6 7 8 | 9
SDA byte:   D7 D6 D5 D4 D3 D2 D1 D0 | ?
Write: fill in the SDA owner for slots 1-8 and slot 9.
Read: fill in the owner and the last-byte response.
Reveal the Model Answer

The controller makes all nine clocks. In the ninth, the transmitter releases SDA. The receiver pulls it low (ACK) and holds it through the high phase; SDA left high is a NACK. On a write the target ACKs, and on a read the controller does. The controller NACKs the last read byte so the target stops driving. An ACK would tell the target to send the next byte, which may hold SDA low and block the STOP.

The Ninth Clock Belongs to the ReceiverA write: the controller transmits both bytes, the target acknowledges each one.
VDD · pull-upSDAControllerctrl_low = pull lowTargettgt_low = pull low

A low lane of 1 pulls the net down. The pull-up raises it only when every device releases.

START0xa0 + ACK0x3c + ACKSTOP 012345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879SCLSDActrl_lowtgt_lowSAAPSDA sampled at 6SDA sampled at 10SDA sampled at 14SDA sampled at 18SDA sampled at 22SDA sampled at 26SDA sampled at 30SDA sampled at 34SDA sampled at 38SDA sampled at 42SDA sampled at 46SDA sampled at 50SDA sampled at 54SDA sampled at 58SDA sampled at 62SDA sampled at 66SDA sampled at 70SDA sampled at 74
Read phases and sample points (quarter bit)
  • START: columns 2 through 3.
  • 0xa0 + ACK: columns 4 through 39.
  • 0x3c + ACK: columns 40 through 75.
  • STOP: columns 76 through 79.
  • SDA sampled at 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74.
  1. Cycle 6

    Clocks 1 to 8: the transmitter (here the controller) drives the bits, most significant first.

  2. Cycle 36

    Clock 9 begins: the controller lets go of SDA. ctrl_low falls to 0.

  3. Cycle 38

    The receiver (the target) pulls SDA low and holds it through the high period: ACK.

  4. Cycle 74

    Every byte has its own ninth clock. A NACK would be nobody pulling: SDA high.

Generated and decoded back. In clocks 1 to 8 the controller drives; in clock 9 it lets go and the target pulls.

  1. Clocks 1 to 8

    The transmitter puts each bit on SDA while SCL is low, MSB first; it is stable while SCL is high.

  2. Clock 9

    The transmitter lets go. The receiver pulls SDA low (ACK) or leaves it high (NACK).

  3. After a NACK

    The controller sends STOP or a repeated START.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Fresher)

A good fresher answer says the receiver drives the ACK, low means ACK, and the controller makes the ninth clock.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

  1. The Ninth Clock: ACK and NACK
  2. WhyWhat a NACK MeansL1 Junior

    Your driver gets a NACK after the address byte. What could it mean, and what should the controller do?

    Reveal the Model Answer

    After an address, most likely no device answers at that address, or the target is busy with a real-time task. Later in a transfer, a NACK can mean the target did not understand the byte or cannot take more. A controller-receiver also NACKs on purpose to end a read. Whatever the reason, the controller ends with STOP or tries again with a repeated START. Software decides whether to retry.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer lists the reasons for a NACK after the address. It gives the controller's two legal answers: STOP, or a repeated START.

    Missed Corner

    "Address 0xA0 got a NACK, so the part is dead."

    Often the datasheet's 0xA0 is the 7-bit address 0x50 shifted left with R/W = 0. Passing 0xA0 to a driver that expects seven bits puts address 0x20 on the wire, and nothing answers.

    Source NXP UM10204 rev. 7 §3.1.10 Figure 10 (seven address bits, then R/W)

  3. Break ItAn ACK That OverstaysL2 Mid-Level

    A target keeps pulling SDA low after its ACK slot, into the next bit. What does a correct controller report, and how do you find the culprit?

    log
    Illustrative SDA ownership excerpt
Ninth clock: target pulls SDA low for ACK
Following data bit: controller releases SDA for a 1
Target still pulls SDA low
Resolved SDA=0
    Reveal the Model Answer

    A correct controller that sends a 1 and reads a 0 decides it lost arbitration. So the log says "arbitration lost", even on a single-controller bus. The wires alone cannot say who pulled. You need the driver view, meaning each device's pull-low enable. It shows the target's lane still active after the ninth clock.

    The ACK That Overstays: ack_not_releasedMeasured on the bench, 100 ns per column, around the address byte's ninth clock and the first bit of the data byte 0xA5.
    VDD · pull-upSDAControllerctrl_low = pull lowTargettgt_low = pull low

    A low lane of 1 pulls the net down. The pull-up raises it only when every device releases.

    01234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465SCLSDActrl_lowtgt_low
    1. Cycle 27

      Clock 9 of the address: the controller has let go; the target pulls. A correct ACK.

    2. Cycle 40

      The SCL fall should end the ACK, but tgt_low stays 1.

    3. Cycle 52

      Bit 7 of 0xA5 is 1, so the controller lets go of SDA. It reads 0 back while SCL is high and concludes it lost arbitration after SCL pulse 10.

    Measured. The target never lets go after its ACK. The controller sends a 1, reads 0 and reports a lost arbitration.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer sees that "arbitration lost" may really be a stuck ACK. It asks to see which device pulls SDA low.

  4. CompareThe I3C T-Bit Versus the I2C ACKL1 JuniorL2 Mid-Level

    In I2C the ninth bit of a data byte is the receiver's ACK. What is it in I3C SDR?

    Reveal the Model Answer

    The transmitter drives it. On a write, it is odd parity from the controller: the XOR of the eight data bits with 1. Parity lets the target detect a corrupted byte. On a read, it is end-of-data from the target: 0 ends the message, and 1 offers more. So the target decides how much it returns, though the controller may abort after a 1 with a repeated START.

    An SDR Private Write: Pointer 0x10, Then 0x3c and 0x01Lanes: SCL and SDA, then who drives SDA low or high, and the drive style. The target only drives in the ACK slots.
    START7e/W (open drain) + ACKSr08/W (push-pull) + ACK10 + T03c + T101 + T0STOP 0123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191SCLSDActrl_lowctrl_hightgt_lowtgt_highdriveodppodppodSASrAT=0T=1T=0PSDA sampled at 6SDA sampled at 10SDA sampled at 14SDA sampled at 18SDA sampled at 22SDA sampled at 26SDA sampled at 30SDA sampled at 34SDA sampled at 38SDA sampled at 46SDA sampled at 50SDA sampled at 54SDA sampled at 58SDA sampled at 62SDA sampled at 66SDA sampled at 70SDA sampled at 74SDA sampled at 78SDA sampled at 82SDA sampled at 86SDA sampled at 90SDA sampled at 94SDA sampled at 98SDA sampled at 102SDA sampled at 106SDA sampled at 110SDA sampled at 114SDA sampled at 118SDA sampled at 122SDA sampled at 126SDA sampled at 130SDA sampled at 134SDA sampled at 138SDA sampled at 142SDA sampled at 146SDA sampled at 150SDA sampled at 154SDA sampled at 158SDA sampled at 162SDA sampled at 166SDA sampled at 170SDA sampled at 174SDA sampled at 178SDA sampled at 182SDA sampled at 186
    Read phases and sample points (quarter bit)
    • START: columns 2 through 3.
    • 7e/W (open drain) + ACK: columns 4 through 39.
    • Sr: columns 40 through 43.
    • 08/W (push-pull) + ACK: columns 44 through 79.
    • 10 + T0: columns 80 through 115.
    • 3c + T1: columns 116 through 151.
    • 01 + T0: columns 152 through 187.
    • STOP: columns 188 through 191.
    • SDA sampled at 6, 10, 14, 18, 22, 26, 30, 34, 38, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126, 130, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174, 178, 182, 186.
    1. Cycle 78

      Header ACK: the target pulls SDA in open drain, exactly as in I2C.

    2. Cycle 79

      Handoff: the controller pulls SDA low just after the SCL rise, while the target lets go. Both low for a moment is safe (MIPI §5.1.2.3.1).

    3. Cycle 114

      Ninth bit of 0x10: the controller drives the parity, XOR(data, 1) = 0. The target drives nothing.

    4. Cycle 150

      Ninth bit of 0x3c: four 1s, so parity 1. Still the controller, still push-pull.

    Generated and decoded back. 0x10 and 0x01 each have one 1 bit, so their T-bit is 0. 0x3c has four 1 bits, so its T-bit is 1.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer says the transmitter drives the T-bit: parity on writes, end-of-data on reads.

    Misconception

    "I3C targets ACK every data byte like I2C."

    Only the address header has an ACK. A target that pulls SDA in the ninth bit of a written byte collides with the controller's push-pull parity bit.

    Source MIPI I3C Basic v1.0 §5.1.2.3.3

  5. What IfA Parity Error on a Written ByteL2 Mid-Level

    What if the target sees a parity error on a byte the controller wrote? What does it do, and how does the controller find out?

    Reveal the Model Answer

    It cannot NACK the byte, because the ninth bit belongs to the controller. Error type S2 says the target ignores the rest and waits for a STOP or a repeated START. The controller sees nothing on the wire. It learns of the error later, from the Protocol Error bit that GETSTATUS returns.

    Self-Check

    Tick each key point you covered in your answer.

    Misconception

    "The target NACKs a bad byte, as in I2C."

    In I3C SDR the controller drives the ninth bit of a write as parity. The target has no slot to answer in.

    Source MIPI I3C Basic v1.0 §5.1.2.3.3

  6. Prove ItSolve P8.3.1: Receive Eight Bits and Own the NinthSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P8.3.1

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"ACKing the last byte is harmless; the STOP ends the read anyway."

An ACK makes the target-transmitter put the next byte's MSB on SDA. If that bit is 0 the target holds SDA low and no STOP can form. The twin shows it, and shows it hiding when the next MSB is 1.

Run It
RUNIcarus Verilog · in your browser
Edit the code, then run it

        
Expected: ACK last byte, next byte 10: read 3c, STOP seen 0, SDA 0 FAIL: no STOP formed, the target still holds SDA ACK last byte, next byte 9a: read 3c, STOP seen 1, SDA 1 PASS: STOP formed

        
        
      

      
See the Fix
`timescale 1ns/1ns
// A one-byte register read, from the first data bit on. The target sends mem[0] and, if the
// controller ACKs, starts mem[1] at once (auto-increment). The controller then tries a STOP:
// SDA low while SCL is low, SCL high, then let go of SDA. A STOP is SDA rising while SCL is high.
module tb;
  logic c_low = 0, t_low = 0, scl = 0;
  wire sda = !(c_low | t_low);
  byte mem [2];
  int stops;
  always @(posedge sda) if (scl) stops++;
  task automatic read_one(input bit ack_last, input byte next);
    byte v; int idx = 0;
    mem[0] = 8'h3c; mem[1] = next; stops = 0;
    for (int b = 7; b >= 0; b--) begin
      #100 t_low = !mem[idx][b];        // the target puts its bit on SDA after the SCL fall
      #1100 scl = 1; #100 v[b] = sda; #1100 scl = 0;
    end
    #100 t_low = 0; c_low = ack_last;   // ninth clock: the controller-receiver answers
    #1100 scl = 1; #1200 scl = 0;
    if (ack_last) begin idx = 1; #100 t_low = !mem[idx][7]; end   // ACKed: the target sends on
    #100 c_low = 1;                     // set up the STOP
    #1000 scl = 1;
    #600 c_low = 0;                     // let go: SDA rises unless the target still pulls
    #1000 if (ack_last) $display("ACK last byte, next byte %h: read %h, STOP seen %0d, SDA %0d", next, v, stops, sda);
    else $display("NACK last byte, next byte %h: read %h, STOP seen %0d, SDA %0d", next, v, stops, sda);
    if (stops == 0) $display("FAIL: no STOP formed, the target still holds SDA");
    else $display("PASS: STOP formed");
    t_low = 0; c_low = 0; #2000 scl = 0;
  endtask
  initial begin
    read_one(0, 8'h10);
    read_one(0, 8'h9a);
    $finish;
  end
endmodule

Prints: NACK last byte, next byte 10: read 3c, STOP seen 1, SDA 1 PASS: STOP formed NACK last byte, next byte 9a: read 3c, STOP seen 1, SDA 1 PASS: STOP formed

    

  

    
Misconception

    
"The target always sends the ACK."

    
The receiver sends it. On a read the controller is the receiver. So it ACKs every byte it wants more of, and NACKs the last.

    
Source NXP UM10204 rev. 7 §3.1.6, §3.1.10

  

    
Half-Truth

    
"A NACK means the bus is broken; reset everything."

    
UM10204 lists five ordinary reasons (no device, busy, not understood, cannot take more, controller ending a read). The answer is a STOP or a repeated START.

  

    
Learn It, Then Prove It