ASIC Point Explore

← Protocols Interviews

Interview Question · Concept

Reading a Register with Repeated START

L0 FresherL1 Juniori2crepeated start

The interviewer asks

Walk me through reading register 0x3C of an I2C target at address 0x50. Why is there a repeated START in the middle?

Reveal the Model Answer

The frame is S, 0x50 with W, ACK, the pointer 0x3C, ACK. Then comes a repeated START, 0x50 with R, ACK, the data byte, NACK, STOP. The write sets the target's internal pointer, and the read returns data from it. The repeated START changes direction without releasing the bus. A STOP would free the bus. On a multi-controller bus, another controller could then take it and move the pointer before the read.

Reading a Register: The Combined FormatWrite the pointer, repeated START, read the data, NACK, STOP.
VDD · pull-upSDAControllerctrl_low = pull lowTargettgt_low = pull low

A low lane of 1 pulls the net down. The pull-up raises it only when every device releases.

START0xa0 + ACK0x3c + ACKSTART0xa1 + ACK0x3c + NACKSTOP 0123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155SCLSDActrl_lowtgt_lowSAASrANAPSDA sampled at 6SDA sampled at 10SDA sampled at 14SDA sampled at 18SDA sampled at 22SDA sampled at 26SDA sampled at 30SDA sampled at 34SDA sampled at 38SDA sampled at 42SDA sampled at 46SDA sampled at 50SDA sampled at 54SDA sampled at 58SDA sampled at 62SDA sampled at 66SDA sampled at 70SDA sampled at 74SDA sampled at 82SDA sampled at 86SDA sampled at 90SDA sampled at 94SDA sampled at 98SDA sampled at 102SDA sampled at 106SDA sampled at 110SDA sampled at 114SDA sampled at 118SDA sampled at 122SDA sampled at 126SDA sampled at 130SDA sampled at 134SDA sampled at 138SDA sampled at 142SDA sampled at 146SDA sampled at 150
Read phases and sample points (quarter bit)
  • START: columns 2 through 3.
  • 0xa0 + ACK: columns 4 through 39.
  • 0x3c + ACK: columns 40 through 75.
  • START: columns 76 through 79.
  • 0xa1 + ACK: columns 80 through 115.
  • 0x3c + NACK: columns 116 through 151.
  • STOP: columns 152 through 155.
  • SDA sampled at 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126, 130, 134, 138, 142, 146, 150.
  1. Cycle 38

    Address 0x50 with W: 0xA0 on the wire. The target acknowledges.

  2. Cycle 74

    The first data byte of a write is the register pointer, here 0x3C (§3.1.10 note 1).

  3. Cycle 78

    Sr, not P: the bus stays busy, so no other controller can move the pointer now.

  4. Cycle 114

    Address 0x50 with R: 0xA1. From here the target drives the data.

  5. Cycle 150

    The register's byte, NACKed by the controller, then STOP.

Generated and decoded back. The bench prints the same transaction: I2C S 50 W A 3c A Sr 50 R A 3c NA P.

S 50 W A 3c A Sr 50 R A <data> NA P

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Fresher)

A good fresher answer gives the frame in order and says who sends each ACK.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

  1. Reading a Register with Repeated START
  2. WhySTOP Plus START Instead of SrL1 Junior

    What concretely goes wrong if you send STOP then START between the pointer write and the read?

    Reveal the Model Answer

    After the STOP and the bus-free time, another controller may win the bus. It may access the same target, move its pointer or change the register. Your read then returns data from the wrong place, with no error anywhere. STOP then START works on a single-controller bus, with a target that keeps its pointer. Sr makes it safe without relying on either assumption.

    Why the Pointer Write and the Read Share One TransactionArrows show bus transactions in time order. With P between them, the bus is free for another controller.
    Why the pointer write and the read share one transactionArrows show bus transactions in time order. With P between them, the bus is free for another controller. component ctrl writespointer 0x3C S 50 W 3c, then P queue Bus free 100 µs of firmware component other writespointer 0x7F S 50 W 7f P component ctrl reads S 50 R: gets register0x7F component With Sr insteadof P the bus never goesfree PSP, SSr
    1. STOP between

      The pointer is written, then P frees the bus. other starts and moves the pointer. The read returns the wrong register: measured value = 7f.

    2. Repeated START

      With Sr the bus stays busy until the read is done; other writes afterwards. Measured: value = 3c.

    Read the diagram as text
    • ctrl writes pointer 0x3C: S 50 W 3c, then P
    • Bus free: 100 µs of firmware
    • other writes pointer 0x7F: S 50 W 7f P
    • ctrl reads: S 50 R: gets register 0x7F
    • With Sr instead of P: the bus never goes free
    • ctrl writes pointer 0x3C → Bus free: P
    • Bus free → other writes pointer 0x7F: S
    • other writes pointer 0x7F → ctrl reads: P, S
    • ctrl writes pointer 0x3C → With Sr instead of P: Sr

    Both runs use the same bench with a second controller that waits for a free bus.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer describes the gap a STOP opens and who can use it: another controller.

  3. What IfA Target That Ignores SrL1 JuniorL2 Mid-Level

    Register writes work, but every combined-format read returns 0xFF. The target ACKs the pointer. What do you suspect?

    log
    Illustrative combined-read decode
START, address+W, ACK, register pointer, ACK
Repeated START, address+R, NACK
Attempted data clocks: SDA remains high (FFh)
    Reveal the Model Answer

    The target does not detect the repeated START. It treats the Sr and the next address byte as more write data, and never answers the read address. So the controller reads the released line: 0xFF. UM10204 requires devices to reset their bus logic on any START or repeated START, and expect an address. A test that only writes, or reads with STOP plus START, never exercises it.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer links the value 0xFF to nobody driving SDA. It suspects the target missed the repeated START.

  4. Prove ItA Test That Exposes a Missed Repeated STARTL1 JuniorL2 Mid-Level

    Prove it: which directed test exposes a target that misses the repeated START?

    Reveal the Model Answer

    A combined-format read: write the register pointer, send Sr, send the read address, then read. Check that the target ACKs the read address and returns the register value, not 0xFF. Cover Sr in the monitor, so coverage shows that this format really ran.

    Self-Check

    Tick each key point you covered in your answer.

    Missed Corner

    "Our read test passes, so repeated START works."

    A read made with STOP and a new START never sends Sr. Only the combined format exercises it.

    Source Lesson P8.4 key points

  5. CompareA 10-Bit Address ReadL2 Mid-Level

    How does a register read change with a 10-bit target address?

    Reveal the Model Answer

    The address takes two bytes: 1111 0XX plus W, then the low eight bits. Here XX are the top two address bits. Several targets may ACK the first byte, but only one ACKs the second. After the pointer write, the controller sends Sr and repeats only the first byte, with R. The target that matched both bytes earlier stays addressed and answers.

    A 10-bit Address: 0x2AAFirst byte 1111 0 10 + W, second byte 0xAA; the read repeats only the first byte, with R.
    VDD · pull-upSDAControllerctrl_low = pull lowTargettgt_low = pull low

    A low lane of 1 pulls the net down. The pull-up raises it only when every device releases.

    START0xf4 + ACK0xaa + ACK0x3c + ACKSTART0xf5 + ACK0x3c + NACKSTOP 0123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191SCLSDActrl_lowtgt_lowSAAASrANAPSDA sampled at 6SDA sampled at 10SDA sampled at 14SDA sampled at 18SDA sampled at 22SDA sampled at 26SDA sampled at 30SDA sampled at 34SDA sampled at 38SDA sampled at 42SDA sampled at 46SDA sampled at 50SDA sampled at 54SDA sampled at 58SDA sampled at 62SDA sampled at 66SDA sampled at 70SDA sampled at 74SDA sampled at 78SDA sampled at 82SDA sampled at 86SDA sampled at 90SDA sampled at 94SDA sampled at 98SDA sampled at 102SDA sampled at 106SDA sampled at 110SDA sampled at 118SDA sampled at 122SDA sampled at 126SDA sampled at 130SDA sampled at 134SDA sampled at 138SDA sampled at 142SDA sampled at 146SDA sampled at 150SDA sampled at 154SDA sampled at 158SDA sampled at 162SDA sampled at 166SDA sampled at 170SDA sampled at 174SDA sampled at 178SDA sampled at 182SDA sampled at 186
    Read phases and sample points (quarter bit)
    • START: columns 2 through 3.
    • 0xf4 + ACK: columns 4 through 39.
    • 0xaa + ACK: columns 40 through 75.
    • 0x3c + ACK: columns 76 through 111.
    • START: columns 112 through 115.
    • 0xf5 + ACK: columns 116 through 151.
    • 0x3c + NACK: columns 152 through 187.
    • STOP: columns 188 through 191.
    • SDA sampled at 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 118, 122, 126, 130, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174, 178, 182, 186.
    1. Cycle 38

      0xF4 = 1111 0 10 0: the 10-bit marker, the top two address bits (10), W. Every 10-bit target with top bits 10 may acknowledge.

    2. Cycle 74

      0xAA: the low eight bits. Only the target at 0x2AA acknowledges this one.

    3. Cycle 114

      To read: Sr, then only the first byte again, now with R (0xF5).

    4. Cycle 186

      The data byte, NACKed by the controller.

    Generated and decoded back. After the repeated START, the read repeats only the first address byte, now with R.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer gives the two-byte 10-bit format. It says only the first byte is repeated after the repeated START.

  6. Break ItWhere an I2C Monitor Closes a TransactionL2 Mid-LevelL3 Senior

    You write an I2C monitor. When does it publish a transaction, and what goes wrong if you publish at START?

    Reveal the Model Answer

    Sample data at SCL rises, and detect START and STOP as SDA edges while SCL is high. Close the current transaction at a repeated START or a STOP. A monitor that publishes at START publishes the previous transaction late. On the first START, it publishes a byte it shifted in before the address. Treat Sr as both the end of one transfer and the start of the next.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer detects START and STOP correctly. It closes a transaction at a repeated START or a STOP.

  7. Prove ItSolve P8.4.1: A Register Target with Repeated STARTSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P8.4.1

What People Get Wrong

Common wrong answers and why they fail.

Half-Truth

"Repeated START is needed because the target forgets the pointer after a STOP."

UM10204 gives the reason as the bus: Sr keeps it busy. Whether a target keeps its pointer across a STOP depends on the device, and many do.

Misconception

"A repeated START is a different signal from a START."

Electrically it is the same SDA fall while SCL is high. The only difference is that no STOP came before it, so the bus stays busy.

Source NXP UM10204 rev. 7 §3.1.4 START and STOP conditions

Learn It, Then Prove It