← Analog & Mixed-Signal Interviews
Interview Question · Debug
A Bias Reference That Never Starts
- Likely at Qualcomm
- Likely at Intel
- Likely at Broadcom
The Question
The interviewer asks
A self-biased beta-multiplier reference shows 9.17 µA in the operating-point run. On the chip it draws almost nothing after power-up. The measurements are below. What happened?
beta multiplier, RS = 10 k, no start-up circuit (measured, ngspice 42, SKY130 tt)
dc sweep of VDD, read at 1.8 V idc = 9.166121e-06 A
power-up transient, read at 40 us itran = 4.804666e-11 AYou have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The circuit has two DC solutions: the working state and a zero-current state where every branch carries nothing. The operating point found the working state. The power-up transient from 0 V stays in the zero state, at about 48 pA. A start-up circuit must push the loop out of zero and then switch itself off. Test it with a supply ramp, at every corner and at the coldest temperature.
- v(vdd)
- i_ref
- Time 10 µsv(vdd) = 1.8 V · i_ref = 138.2 pA
The supply is at 1.8 V. The reference carries 138 pA, pushed through the devices' capacitances by the ramp.
- Time 40 µsv(vdd) = 1.8 V · i_ref = 48.05 pA
48 pA, more than five orders of magnitude short. Nothing is broken.
Read the plot as a table
| Time | v(vdd) | i_ref |
|---|---|---|
| 5 µs | 900 mV | 60.6 pA |
| 10 µs | 1.8 V | 138.2 pA |
| 15 µs | 1.8 V | 67.35 pA |
| 20 µs | 1.8 V | 62.28 pA |
| 25 µs | 1.8 V | 57.94 pA |
| 30 µs | 1.8 V | 54.19 pA |
| 35 µs | 1.8 V | 50.91 pA |
| 40 µs | 1.8 V | 48.05 pA |
The bare reference after a power-up ramp: 48 pA instead of 9.166 µA. The circuit is not broken; it sits in its zero state.
- i_bare
- i_start
- v(x)
- v(vdd)
- Time 4.75 µsi_bare = 58.2 pA · i_start = 43.11 pA · v(x) = -206.3 mV · v(vdd) = 855 mV
At 0.86 V of supply all three start-up devices are off. Node x floats, and charge coupled through the devices pushes it to −0.21 V.
More context
Add
CX x 0 1pto the lab and the dip almost vanishes: a floating node has almost no capacitance of its own, so a little coupled charge moves it a long way. - Time 5.8 µsi_bare = 65.41 pA · i_start = 164.3 nA · v(x) = 659 mV · v(vdd) = 1.044 V
Past 1 V, XS1 conducts and x peaks at 0.69 V. XS2 pulls the PMOS gates down and the started copy takes off.
- Time 7.944 µsi_bare = 87.68 pA · i_start = 8.25 µA · v(x) = 3.959 mV · v(vdd) = 1.43 V
90 % of the final current at 7.94 µs, before the ramp ends. XS3 had pulled x back to millivolts by 6 µs: the kick lasted about half a microsecond.
- Time 40 µsi_bare = 48.04 pA · i_start = 9.166 µA · v(x) = 7.757 mV · v(vdd) = 1.8 V
Settled: 9.166 µA against 48 pA. Node x sits at 7.76 mV, so XS2 is off.
Read the plot as a table
| Time | i_bare | i_start | v(x) | v(vdd) |
|---|---|---|---|---|
| 4.75 µs | 58.2 pA | 43.11 pA | -206.3 mV | 855 mV |
| 5 µs | 60.6 pA | 68.07 pA | -192.3 mV | 900 mV |
| 5.8 µs | 65.41 pA | 164.3 nA | 659 mV | 1.044 V |
| 7.944 µs | 87.68 pA | 8.25 µA | 3.959 mV | 1.43 V |
| 10 µs | 138.2 pA | 9.198 µA | 8.517 mV | 1.8 V |
| 15 µs | 67.02 pA | 9.166 µA | 7.757 mV | 1.8 V |
| 20 µs | 62.07 pA | 9.166 µA | 7.757 mV | 1.8 V |
| 25 µs | 57.81 pA | 9.166 µA | 7.757 mV | 1.8 V |
| 30 µs | 54.11 pA | 9.166 µA | 7.757 mV | 1.8 V |
| 35 µs | 50.86 pA | 9.166 µA | 7.757 mV | 1.8 V |
| 40 µs | 48.04 pA | 9.166 µA | 7.757 mV | 1.8 V |
The same ramp with a start-up circuit: the started copy reaches its working current, and the kick turns itself off.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names the zero-current state. It says an operating-point run cannot find it, but a power-up transient can.
What Interviewers Listen For (Senior)
A good senior answer designs a start-up circuit that turns off after start, and checks the current it keeps drawing. It tests fast and slow ramps at every corner and when cold, where leakage cannot help.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItCompare
- A Bias Reference That Never Starts
-
WhyWhy a Self-Biased Loop Has Two StatesL2 Mid-Level
Why does a self-biased reference have a zero-current state at all?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Each branch's current comes only from the other branch through the mirrors. If one branch carries nothing, the mirror copies nothing to the other, and that is self-consistent. The working state is the second consistent point. Nothing in the circuit prefers one over the other at power-up.
The Beta Multiplier and Its Start-UpLeft and right: the reference of E4.4. Middle: the three start-up devices. Node voltages after start-up. Whole circuit- The working state
Equal currents in both branches; XN2 carries its share with a smaller VGS, and the difference, 91.7 mV, sits across RS: I = 9.17 µA.
9.17 µA · 9.17 µA
- The zero state
Set every current to zero. No current in XP2 means none mirrored into XN1, so XN2 is off and XP2 carries nothing. Every equation holds: the loop can rest here.
- Power-up: x goes high
XS1, a long, weak PMOS with its gate at ground, conducts once the supply passes about 1 V. With the reference off, nothing pulls node x down, so XS1 pulls it up.
- The kick
Node x turns XS2 on. XS2 pulls node b, the PMOS gates, down; the PMOS devices push current into both NMOS devices, and the loop grows it to its working value.
kick
- The kick switches off
Node a rises and turns XS3 on. XS3 is far stronger than XS1, so x falls to a few millivolts and XS2 turns off.
a turns XS3 on
- The price
XS1 keeps conducting into XS3 for as long as the chip is on: 0.639 µA, the start-up's whole cost.
0.639 µA
Read the circuit as text
- XP1 PMOS transistor (4/1): gate →
b, source →VDD, drain →a - XP2 PMOS transistor (4/1): gate →
b, source →VDD, drain →b - XN1 NMOS transistor (2/1): gate →
a, drain →a, source →0 - XN2 NMOS transistor (8/1): gate →
a, drain →b, source →s - RS resistor (10 kΩ): pin 1 →
s, pin 2 →0 - XS1 PMOS transistor (0.5/20): gate →
0, source →VDD, drain →x - XS2 NMOS transistor (1/1): gate →
x, drain →b, source →0 - XS3 NMOS transistor (2/1): gate →
a, drain →x, source →0
a= 0.775 Vb= 0.554 Vs= 91.7 mVx= 7.76 mV
W/L in µm. Bodies tied to sources: NMOS bodies to ground, PMOS bodies to VDD. The local VDD and ground symbols are the same nets as the rails.
Self-Check
Tick each key point you covered in your answer.
- The working state
-
Prove ItSolve E4.7.1: Catch the Bad Bias BlockSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Prove ItShowing the Zero-Current State in SimulationL2 Mid-Level
Prove it: how do you show in simulation that the reference can stick at zero current? The operating point says it works.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
opanddcreport only the working state, so a DC run looks fine. Run a power-up transient from 0 V with a ramped supply. Repeat it at every corner, with fast and slow ramps and at the coldest temperature. Cold leakage is smallest, so a slow ramp there no longer hides the zero state.Self-Check
Tick each key point you covered in your answer.
Tool as Truth
"The operating point shows 20 µA, so it starts."
The solver found one of two solutions. A real power-up can settle in the other one, and only a transient from 0 V shows that.
Source Lesson E4.5 key points
-
CompareBeta Multiplier vs a Resistor BiasL1 JuniorL2 Mid-Level
Compare a beta multiplier with a resistor-into-diode bias on supply sensitivity.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Supply sensitivity is the relative change in current per relative change in supply. A plain resistor gives 1, and a resistor into a diode gave 1.59 in the lesson. The beta multiplier gave 0.241, because a PMOS mirror forces equal currents and the supply enters only through finite r_o. The price is the second, zero-current state.
DC sweepResistor Bias and Beta Multiplier, Each over Its 1.8 V ValueThe resistor bias (n_res) and the base beta multiplier (n_b); 1.0 is each one's current at VDD = 1.8 V. Whole plot- n_res
- n_b
- Supply VDD 1.2 Vn_res = 0.4789 · n_b = 0.3621
At 1.2 V the beta multiplier has only 36 % of its current: it is still starting to conduct.
- Supply VDD 1.434 Vn_res = 0.6792 · n_b = 0.9
From 1.434 V up, the beta multiplier stays within 10 % of its 1.8 V value.
- Supply VDD 1.62 Vn_res = 0.8413 · n_b = 0.973
At −10 % supply: the beta multiplier is 2.7 % low, the resistor bias 15.9 % low.
- Supply VDD 1.98 Vn_res = 1.16 · n_b = 1.021
At +10 %: the beta multiplier is 2.1 % high, the resistor bias 16.0 % high.
Read the plot as a table
Supply VDD n_res n_b 600 mV 0.0362 11 µ 800 mV 0.1589 0.001331 1 V 0.3134 0.04058 1.2 V 0.4789 0.3621 1.4 V 0.6497 0.8544 1.434 V 0.6792 0.9 1.6 V 0.8238 0.9692 1.62 V 0.8413 0.973 1.8 V 1 1 1.98 V 1.16 1.021 2 V 1.178 1.023 Each current over its own 1.8 V value. At ±10 % supply the resistor bias moves about 16 %; the beta multiplier under 3 %.
Self-Check
Tick each key point you covered in your answer.
-
Break ItA Start-Up Circuit That Never Turns OffL2 Mid-LevelL3 Senior
What breaks if the start-up circuit keeps conducting after the reference is running?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
It keeps injecting current into the loop, so the reference current is no longer set only by the resistor. It also burns standing current all the time. Check both on the bench: the reference current with and without the start-up, and the current the start-up branch draws. In the lesson that branch drew 0.64 µA and the reference current did not change.
Self-Check
Tick each key point you covered in your answer.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Tool as Truth
"The operating point shows 9 µA, so the reference works."
An operating point returns one solution. The transient from 0 V stays at 48 pA. With a start-up circuit the same reference reaches 9.17 µA.
Run It
A beta multiplier with no start-up circuit: a DC sweep, then a power-up transient from 0 V.
Run the netlist to draw its plots here.
idc = 9.166121e-06 itran = 4.804666e-11See the Fix
* Two beta multipliers on one supply ramp: X1 bare, X2 with a three-transistor start-up
.lib sky130 tt
.subckt bmult vdd a b s
XP1 a b vdd vdd sky130_fd_pr__pfet_01v8 W=4 L=1
XP2 b b vdd vdd sky130_fd_pr__pfet_01v8 W=4 L=1
XN1 a a 0 0 sky130_fd_pr__nfet_01v8 W=2 L=1
XN2 b a s 0 sky130_fd_pr__nfet_01v8 W=8 L=1
.ends bmult
* dc uses the DC value, 1.8 V; tran ... uic follows the PWL ramp from 0 V
VDD vdd 0 DC 1.8 PWL(0 0 10u 1.8)
X1 vdd a1 b1 s1 bmult
RS1 s1 0 10k
X2 vdd a2 b2 s2 bmult
RS2 s2 0 10k
* start-up for X2: XS1 pulls x up, XS2 kicks b2 low, XS3 switches the kick off
VSU vdd vsu 0
XS1 x 0 vsu vsu sky130_fd_pr__pfet_01v8 W=0.5 L=20
XS2 b2 x 0 0 sky130_fd_pr__nfet_01v8 W=1 L=1
XS3 x a2 0 0 sky130_fd_pr__nfet_01v8 W=2 L=1
.control
dc VDD 0 1.8 0.01
let i_bare = v(s1)/10k
meas dc idc FIND i_bare AT=1.8
tran 0.05u 40u uic
let i_bare = v(s1)/10k
let i_start = v(s2)/10k
meas tran ibare FIND i_bare AT=40u
meas tran istart FIND i_start AT=40u
let rel = i_start/istart
meas tran t90 WHEN rel=0.9 RISE=1
meas tran va FIND v(a2) AT=40u
meas tran vb FIND v(b2) AT=40u
meas tran vx FIND v(x) AT=40u
meas tran isu FIND i(VSU) AT=40u
.endc
.end
Prints: idc = 9.166121e-06 ibare = 4.803593e-11 istart = 9.166134e-06
Missed Corner
"Leakage will kick it out of the zero state anyway."
Leakage can help at a hot corner and fail when cold, where it is smallest. A slow ramp can also hide the zero state. Verify start-up cold, with slow and fast ramps.
Source ASIC Point lesson E4.5