Op-Amps Interview Questions

Two matched transistors share one tail current, I_SS. Their drain currents always add up to I_SS, and the differential input decides how it splits. A small input splits it almost linearly. Past a few hundred millivolts one side carries all of I_SS, so the pair steers current but cannot create more. For a differential signal the tail is an AC ground, and each half acts as a common-source stage.

A differential input raises one gate and lowers the other by the same amount. One drain current rises as the other falls, so the total through the tail does not change. With no change in tail current, the tail voltage does not move. Each half then sees a source held still, like a common-source stage.

No. Both gates rise together, so both currents try to rise and the tail current must change. The tail node then moves with the input. The tail's output resistance limits that change, and that is what gives the pair its common-mode rejection.

Differential gain amplifies the difference between the inputs; common-mode gain is what leaks through when both move together. CMRR is their ratio. Drive both inputs together for A_cm and one input for A_d. The lesson's OTA gave 42.71 dB and -12.66 dB, so 55.37 dB. The hand formula assumes the halves match, but a 5T OTA's output and diode node sit at different voltages.

Too low, and the tail device leaves saturation, so the tail current falls. Too high, and an input device leaves saturation. The lesson's OTA ran from 0.811 V to 1.274 V. DC gain and follower error can hide the lower edge, so check the saturation margins and the tail current directly.

The PMOS mirror copies M1's current change to the output, so the full g_m·v_d reaches one node. DC gain is g_m(r_o2 ∥ r_o4), measured 42.71 dB. The unity-gain frequency is g_m/(2πC_L) and does not depend on r_o: 25.53 MHz here. The gate on the diode side, M1, is the + input. Check that sign open loop, because a buffer with swapped inputs still converges.

The output pole gives -90 degrees. The mirror's diode node adds a second pole, set by its 1/g_m and the gate capacitance of both PMOS devices. That pole sits far above f_u, so it adds only a few degrees there. The lesson measured -95 degrees at f_u.

The pole sits near g_m3 over the gate capacitance of both PMOS devices. At the same current, a wider device adds capacitance faster than it adds g_m. So the pole moves down toward f_u. It then costs more phase at f_u, and the phase margin drops.

The OTA has one high-impedance node, so it is stable by itself. But its gain is one intrinsic gain, 42.71 dB in the lesson. A two-stage op-amp adds a common-source stage, multiplying two gains: 80.84 dB. The second stage gives a second low-frequency pole, so it needs compensation. It also inverts, which moves the + input to the other gate.

Start with f_u and C_L, which give g_m. The current budget then gives g_m/I_D (transconductance per unit current), and a measured chart gives W. The gain sets the length, and the input range checks the tail and the load. Keep margin on f_u, because the output node carries more than C_L. Check every line at every input level the brief names.

This is systematic offset, built into the schematic. In a 5T OTA the output and the diode node sit at different voltages. So the two halves are not in the same state. The offset is about -(V_out - V_x)/A_0, -2.04 mV by hand against -2.17 mV measured. Silicon adds random offset from device mismatch, different on every chip. It shrinks with device area.

A threshold error ΔV in a load device changes its current by g_m,load·ΔV. To cancel that current, the input pair needs a differential input that changes its current by the same amount. That input is g_m,load·ΔV divided by g_m,pair. So the load's error reaches the input scaled by the ratio of the two transconductances.

Give every transistor in every copy its own random draw. In sky130, turn mismatch on with MC_MM_SWITCH=1 and fix the seed, so the run repeats. Report the mean and σ. The mean is the systematic offset plus a small sampling error. Sign off at the mean plus or minus 3σ, not at the worst die you happened to sample. In the lesson 30 dies gave a mean of -2.62 mV and σ of 1.83 mV.

Random variations in doping and edges average out over a larger gate. For a pair, σ of the threshold difference is A_VT divided by √(W·L). Four times the area halves it. For sky130 the lesson found A_VT of about 4.75 mV·µm for the NMOS and 8.28 mV·µm for the PMOS.

The threshold error comes from many small random events, such as single dopant atoms, spread over the gate. Their number grows with the area. The spread of a sum of random events grows only as its square root. Averaged over the area, the error therefore falls as 1/√(W·L).

Grow the pair whose share dominates the offset. Each pair's part adds as a power: the input pair one to one, the load mirror scaled by g_m3/g_m1. Four times the area of every device halves σ. Sixteen times the area of one pair leaves the other pair's part untouched, so it helps only if that pair dominated.

Yes. A process corner moves every transistor of a type together, the global spread between wafers. Mismatch moves each transistor alone, the local spread on one die. Offset comes mostly from mismatch, while bias currents and speed move mostly with corners. Sign-off runs corners crossed with supply and temperature, plus Monte Carlo.

The second stage sets the first stage's output voltage. If that voltage differs from the diode node, the first stage is unbalanced, and the offset is about (V_o1 - V_x)/A_1. Size the devices so that (W/L)_6/(W/L)_4 = 2(W/L)_7/(W/L)_5. Then the first-stage output sits at V_x.

A large input steers the whole tail current to one side. On the rising edge the first stage charges C_c with that current, so SR = I_SS/C_c, 18.0 V/µs. On the falling edge, M7 must discharge C_L and also take C_c's current. That gives about (I_7 - I_SS)/C_L, 11.0 V/µs by hand against 11.1 measured. A small signal never slews.

A small step unbalances the pair a little, so its output current grows with the input and the response is linear. A large step steers the whole tail current to one side. After that the current cannot grow, so C_c charges at a fixed rate. The output becomes a ramp, not an exponential.

The small-signal bandwidth limits any signal by frequency. The slew rate limits large signals: a sine of amplitude A needs a slope of 2πfA. Above the full-power bandwidth, SR/(2πA), the output turns into a triangle. A large output swing can therefore distort far below f_u.

Phase margin is 180 degrees plus the phase of the loop gain at the frequency where its magnitude is 1. At 0 degrees or less, the loop oscillates. Less margin means more overshoot and ringing on a step. Near 60 degrees a step settles fastest, so 60 to 70 degrees is the usual target. A buffer is the hardest case, because all of the output feeds back.

The loop gain is the op-amp gain times the feedback factor β. In a buffer β is 1, so the loop gain is largest and crosses 1 at the highest frequency, closest to the second pole. As a gain-of-two amplifier, β is one half. The same op-amp then went from 27.3 to 37.4 degrees of margin.

To ground, it loads the input with its own value. Across an inverting gain of -A, the far end moves A times as much the other way. So it draws (1 + A) times the current and acts like C(1 + A) at the input. In the lesson, 20 fF across the stage cut the bandwidth from 98.9 to 8.5 MHz.

C_c splits the poles: it lowers the first pole and pushes the output pole up toward g_m6/(2πC_L). But C_c also feeds the signal forward to the output. That makes a right-half-plane zero at g_m6/(2πC_c), which lags the phase like a pole. A series R_z moves the zero. With R_z = 1/g_m6 it disappears, and a larger R_z turns it into phase lead.

A left-half-plane zero adds phase lead as the gain rises. A right-half-plane zero raises the gain in the same way but adds phase lag instead. So it costs margin like a pole while it slows the gain's fall. In a Miller op-amp it comes from current that C_c passes forward from the first stage to the output.

At the zero, the current that C_c feeds forward equals the current the second stage sinks, so they cancel at the output. The forward current grows with frequency as s·C_c, and the stage current is set by g_m6. They meet at g_m6/(2πC_c). A bigger C_c lowers this zero, and it lowers f_u by the same factor.

The zero moves out to a very high frequency, so it no longer lags the phase. On this op-amp the margin rises from 27.3 to 45.1 degrees. That is better but still short of 60, because the output pole is still close to f_u. A slightly larger R_z, here 5 kΩ, puts a helpful zero near that pole.

With the zero cancelled, f_u must stay below the output pole divided by 2.2. In the lesson that capped the op-amp at 5.77 MHz, and 10 MHz needed 2.5 times the second-stage current. Placing a left-half-plane zero near the worst output pole met the brief at the original current, with 1.75 pF and 8 kΩ. The price is sensitivity to R_z and to the load.

Cutting the loop removed the DC feedback that held the bias. So the output fell to 0.145 V, and the op-amp left its working state. A loop-gain bench must keep the DC bias and every load at the break point. A large inductor and capacitor break the loop for AC only. Middlebrook's method keeps the loop closed and combines a voltage run and a current run.

Breaking the loop removes the load that one side of the break saw. At a stiff output driving a gate, that load was tiny, so nothing changes. Where the source impedance is high or the load is heavy, removing the load changes the gain and the poles. Then the measured margin is wrong.

The inductor-and-capacitor break is one simple run, but it is exact only at a stiff node. Middlebrook's method keeps the loop closed and every load in place. It injects a series voltage in one run and a shunt current in another, then combines the two results. It works at any point in the loop, at the cost of two runs and a formula.