Noise and Mixed-Signal Interview Questions

The total noise is √(kT/C), about 64.4 µV rms for 1 pF at 27 °C. A bigger resistor makes more noise per hertz, 4kTR. But it also narrows the bandwidth, 1/(4RC) in noise terms, by the same factor. The two cancel, so only C sets the total. To halve the noise you need four times the capacitance.

The noise density is 4kTR, so ten times R gives ten times the power per hertz. The RC filter's noise bandwidth is 1/(4RC), so ten times R gives a tenth of the bandwidth. The total is density times bandwidth, 4kTR · 1/(4RC) = kT/C. The R cancels.

A first-order filter does not cut off sharply. Its response falls slowly past the corner, so noise above f_-3dB still gets through. Integrating the whole curve gives the same total as a sharp filter π/2 times wider. That width is 1/(4RC), against 1/(2πRC) for the corner.

Each extra bit halves the quantization step, so the sampled noise must halve too. Noise goes as one over the square root of C, so each bit needs four times the capacitance. A bigger sampling capacitor also needs more drive current to charge in the same time. That makes kT/C a power limit for high-resolution converters.

kT/C noise is random and set only by the hold capacitor, about 64 µV on 1 pF. Charge injection is a step left when the switch opens: channel charge and clock feedthrough land on the capacitor. It grows with switch width, falls with C_H, and depends on the input, so it is distortion, not just offset. A half-width dummy switch on the inverted clock cancels most of it.

Input-referred noise is output noise divided by gain, so amplifiers with different gains can be compared fairly. In a 5T OTA the input pair dominates. The load mirror adds its noise scaled by g_m3/g_m1, and the tail cancels as common mode. Here flicker noise dominates up to about 939 kHz. Above that, the thermal floor needs the model's γ, about 2 for the NMOS pair, not the textbook 2/3.

Tail noise changes the current in both halves of the pair equally. That is a common-mode change. The OTA rejects common mode, so the tail noise barely reaches the differential output. It returns if the halves are badly mismatched.

Each load device's noise current flows into one side of the OTA only. So it is a differential signal, and the OTA does not reject it. Referred to the input, the load's noise appears scaled by g_m3/g_m1. A smaller g_m3/g_m1 lowers its share.

Thermal noise is white, 4kTγg_m in the channel, and falls when g_m rises. Flicker noise falls with frequency and with gate area. The flicker corner is where the two meet. In the lesson, 16 times the area moved the corner from 1.29 MHz to 48 kHz. Read a device's noise over the band you use, because a 100 kHz number says nothing about 10 Hz.

Independent noise sources add as powers, so write the budget in squared volts. Refer every stage to the input by dividing by the gain in front of it. The first stage usually dominates, so give it most of the budget and enough gain. Size the sampling capacitor from kT/C. Check the total over the real signal band, flicker included.

Give every transistor in every copy its own random draw. In sky130, turn mismatch on with MC_MM_SWITCH=1 and fix the seed, so the run repeats. Report the mean and σ. The mean is the systematic offset plus a small sampling error. Sign off at the mean plus or minus 3σ, not at the worst die you happened to sample. In the lesson 30 dies gave a mean of -2.62 mV and σ of 1.83 mV.

Random variations in doping and edges average out over a larger gate. For a pair, σ of the threshold difference is A_VT divided by √(W·L). Four times the area halves it. For sky130 the lesson found A_VT of about 4.75 mV·µm for the NMOS and 8.28 mV·µm for the PMOS.

The threshold error comes from many small random events, such as single dopant atoms, spread over the gate. Their number grows with the area. The spread of a sum of random events grows only as its square root. Averaged over the area, the error therefore falls as 1/√(W·L).

Grow the pair whose share dominates the offset. Each pair's part adds as a power: the input pair one to one, the load mirror scaled by g_m3/g_m1. Four times the area of every device halves σ. Sixteen times the area of one pair leaves the other pair's part untouched, so it helps only if that pair dominated.

Yes. A process corner moves every transistor of a type together, the global spread between wafers. Mismatch moves each transistor alone, the local spread on one die. Offset comes mostly from mismatch, while bias currents and speed move mostly with corners. Sign-off runs corners crossed with supply and temperature, plus Monte Carlo.

A schematic Monte Carlo sees only random mismatch. Layout adds gradients and edge effects, which depend on position and shift every die of a wafer the same way. Under a linear gradient, offset equals the gradient times the distance between the devices' centres. A common-centroid pattern such as ABBA makes that distance zero. Dummy fingers at the ends remove the edge effect.

A linear gradient shifts each finger by an amount proportional to its position. In ABBA, the A fingers sit at both ends and the B fingers in the middle. Both devices then have their average position, their centroid, at the same point. So the gradient shifts both by the same amount, and the difference cancels.

Random mismatch is different on every die and falls with area, so bigger devices help. Systematic errors from gradients and edges shift every die the same way. They depend on where the devices sit, so more area alone may not help. Placement fixes them: common centroid, dummies and the same orientation.

Ask for every specification line with its measured margin at every corner, crossed with supply and temperature. Ask for Monte Carlo mean plus or minus 3σ on offset and matching. Check stability at the worst load and feedback factor, with a step as well as a margin. Check start-up with supply ramps, fast and cold-slow. Finally, ask which known faults the benches were shown to catch.

A bench that passes everything may not be measuring what you think. Insert known faults, such as a missing R_z, a starved bias or a swapped input. A good bench fails each one with a clear reason. In the lesson, DC-level checks missed both a missing R_z and a starved bias.

Plant faults that a weak bench would miss. Remove R_z: the step settling check at speed must show ringing. Starve the bias: the input-range check at speed must fail near the top code. Swap the inputs: the open-loop sign check must fail. Each check that never fails is measuring nothing useful.

Write each requirement as one line with a limit and a measurement, set after measuring a reference design at every corner. Use one bench per check. Run a supply sweep and a temperature and supply sweep for the worst case. Add an output sweep for compliance and power-up transients, fast and slow. A constant-g_m reference moves its current on purpose, so specify the tail current as a band.

A corner can push an edge of the input range past the top or bottom code. Then the buffer's tail leaves saturation at that code and the output error jumps. Choose the DAC references inside the buffer's range at speed, not just where the DC error is small. Check them at every corner.

The latch amplifies the small input difference by positive feedback, so it grows as e^(t/τ). The time constant τ is about C/g_m of the cross-coupled inverters. The decision time is τ times the log of the ratio between the full swing and the starting difference. Each tenfold smaller input adds ln 10 · τ, 105 ps in the lesson. As the input goes to zero, the time has no limit.

Each inverter drives the other's input. A small difference makes each one push its output further apart, and the rate of growth is proportional to the difference itself. Growth proportional to size is exponential growth. The time constant is the node capacitance over the inverter g_m.

The difference grows as v_0·e^(t/τ), so a ten times smaller start needs ln 10 times τ more. In the lesson that was 105 ps per decade, with τ = 45.6 ps. There is no upper limit: an input near zero can take any length of time. That is metastability, and it sets the comparator's error rate.

They are the same physics. A flip-flop sampling a changing input is a latch that starts from a tiny difference. The undecided window shrinks as e^(-t/τ) with the time allowed to settle. That is why MTBF grows exponentially with settling time, and why synchronizers add a whole clock period of settling.

A strong answer starts from the specification lines and the margins you set. It explains the sizing method with one or two real numbers. An example is g_m/I_D charts, which plot transconductance per unit current against current density. It tells one problem in detail, such as poor phase margin at the heaviest load, with what you tried and what worked. It ends with the evidence: corners, Monte Carlo, start-up and post-layout results.

A good story names the effect, such as extra parasitic capacitance that cut phase margin or a gradient that added offset. It shows how it was found, by post-layout simulation or measurement, and how it was fixed. It ends with what changed in the method, such as margins kept for parasitics or common-centroid placement planned from the start.

High g_m/I_D, near weak inversion, gives the most transconductance per microamp. But the device is wide and slow, and its threshold mismatch becomes a larger current error. Low g_m/I_D, strong inversion, costs current but gives small, fast devices and better current matching. Input pairs often sit high for noise and offset; mirrors and fast stages sit lower.