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Interview Question · Design
Designing a Wide-Swing Cascode Mirror
The Question
The interviewer asks
A differential pair's tail must stay accurate down to a low output voltage. You choose a wide-swing cascode mirror. How do you size its bias, and how do you check it?
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Reveal the Model Answer
A separate diode device biases the cascode gates. It is sized so the bottom devices sit just above V_Dsat. The textbook W/4 rule comes from the square law, and in sky130 it left the copy 12 % low. A cascode on the reference side makes both bottom devices see the same V_DS and fixes the copy. Then sweep the output to find where the current is 1 % low, at every corner.
- The bias device sets b
XB is an eighth of the 8 µm width. At 20 µA it needs a larger VGS, so the bias line b sits at 1.014 V.
20 µA
- The cascodes hold y and x low
R2 and O2 have their gates on b, so their sources sit one VGS lower: y = 0.245 V and x = 0.246 V. Both bottom devices get about 0.25 V, above their 0.137 V VDsat.
- The bottom devices match
R1's gate is tied to g, the top of the reference branch, so g settles where R1 carries 20 µA at y. O1 shares g and sits at nearly the same VDS: it copies 20.006 µA at 0.9 V.
20.006 µA
- Room at the output
O2 needs only its own VDsat above x, so the output can fall to 0.297 V before the current is 1 % low.
Read the circuit as text
- IB current source (20 µA): + →
VDD, − →b - XB NMOS transistor (1/1): gate →
b, drain →b, source →0 - IREF current source (20 µA): + →
VDD, − →g - R2 NMOS transistor (8/1): gate →
b, drain →g, source →y - R1 NMOS transistor (8/1): gate →
g, drain →y, source →0 - O2 NMOS transistor (8/1): gate →
b, drain →n1, source →x - O1 NMOS transistor (8/1): gate →
g, drain →x, source →0 - out port: terminal →
n1
b= 1.014 Vg= 0.718 Vy= 0.245 Vx= 0.246 V
Node voltages at Vout = 0.9 V from the lab's mirror m8. Widths in µm, all L = 1 µm; all bodies are the substrate at ground.
- i_s
- i_c
- i_w4
- i_m8
- Output voltage VO 300 mVi_s = 19.16 µA · i_c = 19.11 µA · i_w4 = 17.37 µA · i_m8 = 19.81 µA
At 0.3 V the matched W/8 mirror already gives 19.81 µA. The simple and the stacked mirrors give about 19.1 µA, the W/4 mirror 17.4 µA.
- Output voltage VO 900 mVi_s = 20.27 µA · i_c = 19.99 µA · i_w4 = 17.55 µA · i_m8 = 20.01 µA
At 0.9 V: simple 20.27 µA, stacked 19.99 µA, W/4 17.55 µA, matched W/8 20.006 µA.
- Output voltage VO 1.7 Vi_s = 21.26 µA · i_c = 20 µA · i_w4 = 17.64 µA · i_m8 = 20.02 µA
At 1.7 V the simple mirror has climbed to 21.26 µA; the cascodes have hardly moved.
Read the plot as a table
| Output voltage VO | i_s | i_c | i_w4 | i_m8 |
|---|---|---|---|---|
| 0 V | 0 A | 0 A | 0 A | 0 A |
| 200 mV | 18.64 µA | 18.51 µA | 16.67 µA | 19 µA |
| 300 mV | 19.16 µA | 19.11 µA | 17.37 µA | 19.81 µA |
| 400 mV | 19.44 µA | 19.39 µA | 17.45 µA | 19.97 µA |
| 600 mV | 19.82 µA | 19.76 µA | 17.5 µA | 20 µA |
| 800 mV | 20.13 µA | 19.97 µA | 17.53 µA | 20 µA |
| 900 mV | 20.27 µA | 19.99 µA | 17.55 µA | 20.01 µA |
| 1 V | 20.4 µA | 19.99 µA | 17.56 µA | 20.01 µA |
| 1.2 V | 20.66 µA | 20 µA | 17.58 µA | 20.01 µA |
| 1.4 V | 20.9 µA | 20 µA | 17.61 µA | 20.02 µA |
| 1.6 V | 21.14 µA | 20 µA | 17.63 µA | 20.02 µA |
| 1.7 V | 21.26 µA | 20 µA | 17.64 µA | 20.02 µA |
| 1.8 V | 21.38 µA | 20 µA | 17.65 µA | 20.03 µA |
Four 20 µA mirrors swept. The W/4 mirror is flat but 12 % low; the matched W/8 mirror is right and works down to about 0.3 V.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains how the extra diode device sets the cascode bias. It checks the copy and the lowest output voltage by sweeping the output.
What Interviewers Listen For (Senior)
A good senior answer uses the bias width to trade output resistance against the lowest output voltage. It adds a reference-side cascode for accuracy, and checks every corner.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompareScale It
- Designing a Wide-Swing Cascode Mirror
-
WhyWhy a Reference-Side Cascode Fixes the CopyL2 Mid-Level
Why does adding a cascode on the reference side make the wide-swing copy accurate?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
In the plain wide-swing mirror the reference device is diode-connected, so its V_DS is V_GS. The output's bottom device sits near V_Dsat instead. Different V_DS means a different current. A cascode on the reference side holds its bottom device at the same low V_DS as the output side. Then both carry the same current.
DC sweepA Wide-Swing Mirror Sized by the W/4 RuleOutput current against output voltage. Every device is W/L = 8/1 µm except the 2/1 µm bias device. Whole plot- Output voltage VO 900 mVi_w4 = 17.55 µA
At 0.9 V the copy is 17.55 µA: a flat curve, at the wrong current.
- Output voltage VO 1.7 Vi_w4 = 17.64 µA
At 1.7 V it is still only 17.64 µA. A high output resistance holds an error as faithfully as a correct current.
Read the plot as a table
Output voltage VO i_w4 0 V 0 A 200 mV 16.67 µA 400 mV 17.45 µA 600 mV 17.5 µA 800 mV 17.53 µA 900 mV 17.55 µA 1 V 17.56 µA 1.2 V 17.58 µA 1.4 V 17.61 µA 1.6 V 17.63 µA 1.7 V 17.64 µA 1.8 V 17.65 µA The wide-swing mirror without a reference-side cascode: a flat curve at the wrong current, 17.55 µA instead of 20 µA.
Self-Check
Tick each key point you covered in your answer.
- Output voltage VO 900 mVi_w4 = 17.55 µA
-
Prove ItSolve E4.3.1: The Leanest Wide-Swing SinkSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
What IfSizing the Wide-Swing Bias by the Square LawL2 Mid-LevelL3 Senior
What if you size the cascode bias device by the square-law W/4 rule instead of sweeping? What happens in sky130?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
In the lesson the W/4 rule left the copy 12 % low. Short sky130 devices do not follow the square law, so the bottom devices end up at the wrong V_DS. The bias width trades output resistance against the lowest output voltage. So find it by sweeping, and check the copy at the target output range.
Self-Check
Tick each key point you covered in your answer.
Misconception
"W/4 is exact; the textbook derives it."
The derivation assumes the square law. Short devices break that model, so the derived width puts the bottom devices at the wrong voltage.
Source Lesson E4.3 key points
-
CompareSimple Mirror vs Cascode MirrorL1 JuniorL2 Mid-Level
Compare a simple mirror with a cascode mirror.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A cascode device on top raises the output resistance by about (g_m + g_mb)·r_o. In the lesson it went from 0.80 MΩ to 102 MΩ. The price is headroom: the output now needs about V_GS + V_Dsat, around 0.85 V. A wide-swing version gets most of the gain back while the output can fall to about 0.3 V.
Self-Check
Tick each key point you covered in your answer.
-
Scale ItWriting a Bias Block SpecificationL3 Senior
You must hand over a bias block to other designers. How do you write its specification and prove it?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Write each requirement as one line with a limit and a measurement, set after measuring a reference design at every corner. Use one bench per check. Run a supply sweep and a temperature and supply sweep for the worst case. Add an output sweep for compliance and power-up transients, fast and slow. A constant-g_m reference moves its current on purpose, so specify the tail current as a band.
The Bias Block, Piece by PieceArrows show where a current or a gate voltage goes. W/L in µm. Illustrative sequence- Reference and start-up
The beta multiplier of E4.4 sets 10 µA with a
res_high_poresistor (W = 0.35 µm, L = 8.54 µm). The start-up of E4.5 kicks it on at power-up and then switches off. - Send currents
PMOS devices on the reference's gate line b copy its current: 10 µA for the NMOS reference stack and 2.5 µA for the cascode bias. Currents travel; gate voltages stay local (E4.2).
- Wide-swing cascode
The 2.5 µA diode XBC sets the cascode gate c. The reference stack sets the bottom gate g with its own cascode, so both bottom devices see the same drain voltage (E4.3). The tail is two units of the stack: 20 µA.
- PMOS bias output
One more unit on gate g sinks 10 µA from a diode-connected 8/1 PMOS. Its gate is
pbias: any 8/1 PMOS with its source at VDD and this gate voltage sources about 10 µA.
Read the diagram as text
- Start-up: XS1-XS3: kick at power-up, then off
- Reference: Beta multiplier, K = 4, RS a res_high_po: 10 µA
- PMOS copies: XP3 4/1: 10 µA; XP4 1/1: 2.5 µA
- Cascode bias: XBC 0.5/1.5 diode sets node c
- Reference stack: XC1 over XB1, 16/1 units: node g
- Tail output: XC2 over XB2, two units: 20 µA
- PMOS bias output: XB3 sinks 10 µA from XPB 8/1
- Start-up → Reference: kick
- Reference → PMOS copies: gate b
- PMOS copies → Cascode bias: 2.5 µA
- PMOS copies → Reference stack: 10 µA
- Cascode bias → Tail output: gate c
- Reference stack → Tail output: gate g
- Reference stack → PMOS bias output: gate g
The full netlist is the Try it below. Units are whole devices (
m=2for the tail), so the 2:1 ratio does not depend on drawn widths matching.Self-Check
Tick each key point you covered in your answer.
- Reference and start-up
What People Get Wrong
Common wrong answers and why they fail.
Half-Truth
"Use the W/4 rule for the bias device and you are done."
The rule comes from the square law. In sky130 it left the copy 12 % low. Find the bias width by sweeping, not from the ratio.
Source ASIC Point lesson E4.3 (measured)
Buzzword Without Mechanism
"The minimum output voltage is two V_Dsat."
That is a hand estimate. The lesson defines it as the voltage where the current falls 1 % below its value at 0.9 V, and measures it.
Source ASIC Point lessons E4.1 and E4.3