A Latched Comparator's Decision Time

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompare

1. A Latched Comparator's Decision Time
2. WhyWhy Regeneration Is ExponentialL1 JuniorL2 Mid-Level

   Why does the difference in a cross-coupled latch grow exponentially?

   Reveal the Model Answer

   Each inverter drives the other's input. A small difference makes each one push its output further apart, and the rate of growth is proportional to the difference itself. Growth proportional to size is exponential growth. The time constant is the node capacitance over the inverter g_m.

   1. Reset

      With the clock low, M0 is off and S1-S4 pull outn, outp, p and q to 1.8 V. Nothing conducts from VDD to ground, so the latch draws no current while it waits.

   2. Integrate

      The clock rises: S1-S4 open and M0 turns on. M1 and M2 discharge p and q, and the side with the higher input discharges a little faster.

      I₁ > I₂

   3. Regenerate

      Once p and q are low enough, M3 and M4 conduct and both outputs fall. Each output drives the other inverter, so the one falling faster turns the other side's pull-up on.

   4. Decided

      One output reaches ground and the other returns to 1.8 V. With inp above inn, outp ends high. The current stops: a decided latch draws no static current either.

   Read the circuit as text

   • S1 PMOS transistor (1/0.15): gate → n1, source → VDD, drain → outn
   • M5 PMOS transistor (2/0.15): gate → outp, source → VDD, drain → outn
   • M6 PMOS transistor (2/0.15): gate → outn, source → VDD, drain → outp
   • S2 PMOS transistor (1/0.15): gate → n2, source → VDD, drain → outp
   • M3 NMOS transistor (2/0.15): gate → outp, drain → outn, source → p
   • M4 NMOS transistor (2/0.15): gate → outn, drain → outp, source → q
   • S3 PMOS transistor (1/0.15): gate → n3, source → VDD, drain → p
   • S4 PMOS transistor (1/0.15): gate → n4, source → VDD, drain → q
   • M1 NMOS transistor (4/0.15): gate → n5, drain → p, source → n6
   • M2 NMOS transistor (4/0.15): gate → n7, drain → q, source → n6
   • M0 NMOS transistor (4/0.15): gate → n8, drain → n6, source → 0
   • inp port: terminal → n5
   • inn port: terminal → n7
   • clk port: terminal → n8
   • clk port: terminal → n1
   • clk port: terminal → n2
   • clk port: terminal → n3
   • clk port: terminal → n4

   W/L in µm. NMOS bodies at ground, PMOS bodies at VDD. The lab adds 10 fF from each output to ground.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Each inverter drives the other's input. Key point 2 A small difference makes each one push its output further apart, and the rate of growth is proportional to the difference itself. Key point 3 Growth proportional to size is exponential growth. Key point 4 The time constant is the node capacitance over the inverter g_m.

   • Lesson E8.1The Comparator and Its Decision Time
3. What IfA Ten Times Smaller Comparator InputL1 JuniorL2 Mid-Level

   What if the input difference is ten times smaller? How much longer does the decision take?

   Reveal the Model Answer

   The difference grows as v_0·e^(t/τ), so a ten times smaller start needs ln 10 times τ more. In the lesson that was 105 ps per decade, with τ = 45.6 ps. There is no upper limit: an input near zero can take any length of time. That is metastability, and it sets the comparator's error rate.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The difference grows as v_0·e^(t/τ), so a ten times smaller start needs ln 10 times τ more. Key point 2 In the lesson that was 105 ps per decade, with τ = 45.6 ps. Key point 3 There is no upper limit: an input near zero can take any length of time. Key point 4 That is metastability, and it sets the comparator's error rate.

   Missed Corner

   "A tiny input just gives a slightly late decision."

   The delay grows with the log of one over the input, without bound. A decision read before it settles gives a wrong or undefined code.

   Source Lesson E8.1 key points

   • Lesson E8.1The Comparator and Its Decision Time
   • Problem E8.1.1A Faster Decision
4. CompareComparator Decisions vs Flip-Flop MetastabilityL2 Mid-LevelL3 Senior

   Compare a comparator's slow decision with flip-flop metastability.

   Reveal the Model Answer

   They are the same physics. A flip-flop sampling a changing input is a latch that starts from a tiny difference. The undecided window shrinks as e^(-t/τ) with the time allowed to settle. That is why MTBF grows exponentially with settling time, and why synchronizers add a whole clock period of settling.

   • v(outp)
   • v(outn)
   • difference

   1. Time 318.1 psv(outp) = 900 mV · v(outn) = 900 mV · difference = 28.6 µV

      Both outputs cross 0.9 V together, 208 ps after the clock. The difference is still almost zero.

   2. Time 483 psv(outp) = 849.8 mV · v(outn) = 848.7 mV · difference = 1.048 mV

      outp bottoms out at 0.850 V, then turns back up: the latch is deciding.

   3. Time 803.4 psv(outp) = 1.301 V · v(outn) = 401.2 mV · difference = 900 mV

      The difference reaches 0.9 V at 693 ps. That is the decision time.

   Read the plot as a table

   Time	v(outp)	v(outn)	difference
   0 s	1.8 V	1.8 V	37.75 fV
   318.1 ps	900 mV	900 mV	28.6 µV
   483 ps	849.8 mV	848.7 mV	1.048 mV
   500 ps	849.9 mV	848.4 mV	1.522 mV
   803.4 ps	1.301 V	401.2 mV	900 mV
   1 ns	1.794 V	5.664 mV	1.789 V
   1.5 ns	1.803 V	1.793 V	10.23 mV
   2 ns	1.8 V	1.8 V	1.927 µV

   A 1 µV input: both outputs fall together before one wins. A flip-flop near metastability waits the same way.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 They are the same physics. Key point 2 A flip-flop sampling a changing input is a latch that starts from a tiny difference. Key point 3 The undecided window shrinks as e^(-t/τ) with the time allowed to settle. Key point 4 That is why MTBF grows exponentially with settling time, and why synchronizers add a whole clock period of settling.

   • Lesson E8.1The Comparator and Its Decision Time
   • Lesson R6.1Metastability and MTBF
5. Prove ItSolve E8.1.1: A Faster DecisionSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem E8.1.1

6. What IfkT/C Noise vs Charge Injection in a Sample-and-HoldL1 JuniorL2 Mid-Level

   Asked if the comparator follows a sample-and-hold

   Compare kT/C noise with charge injection as errors of a sample-and-hold switch.

   Reveal the Model Answer

   kT/C noise is random and set only by the hold capacitor, about 64 µV on 1 pF. Charge injection is a step left when the switch opens: channel charge and clock feedthrough land on the capacitor. It grows with switch width, falls with C_H, and depends on the input, so it is distortion, not just offset. A half-width dummy switch on the inverted clock cancels most of it.

   • input 0.2 V
   • input 0.5 V
   • input 0.8 V
   • clock

   1. Time 900 psinput 0.2 V = -201.2 pV · input 0.5 V = -741.1 pV · input 0.8 V = -4.223 nV · clock = 1.8 V

      Tracking: each hold node equals its input, so every error is zero.

   2. Time 1.1 nsinput 0.2 V = -903.2 µV · input 0.5 V = -734.8 µV · input 0.8 V = -575.7 µV · clock = 0 V

      The gate falls in 0.1 ns and the switch opens. Each hold node jumps down.

   3. Time 3 nsinput 0.2 V = -903.3 µV · input 0.5 V = -734.9 µV · input 0.8 V = -575.8 µV · clock = 0 V

      Held: −0.903 mV at 0.2 V, −0.735 mV at 0.5 V, −0.576 mV at 0.8 V. The step shrinks as the input rises.

   Read the plot as a table

   Time	input 0.2 V	input 0.5 V	input 0.8 V	clock
   0 s	-201.2 pV	-741.1 pV	-4.311 nV	1.8 V
   500 ps	-201.2 pV	-741.1 pV	-4.26 nV	1.8 V
   900 ps	-201.2 pV	-741.1 pV	-4.223 nV	1.8 V
   1 ns	-201.2 pV	-741.1 pV	-4.215 nV	1.8 V
   1.1 ns	-903.2 µV	-734.8 µV	-575.7 µV	0 V
   1.5 ns	-903.3 µV	-734.9 µV	-575.8 µV	0 V
   2 ns	-903.3 µV	-734.9 µV	-575.8 µV	0 V
   2.5 ns	-903.3 µV	-734.9 µV	-575.8 µV	0 V
   3 ns	-903.3 µV	-734.9 µV	-575.8 µV	0 V

   Charge injection, measured: when the switch opens, each held voltage jumps by a step that depends on the input.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 kT/C noise is random and set only by the hold capacitor, about 64 µV on 1 pF. Key point 2 Charge injection is a step left when the switch opens: channel charge and clock feedthrough land on the capacitor. Key point 3 It grows with switch width, falls with C_H, and depends on the input, so it is distortion, not just offset. Key point 4 A half-width dummy switch on the inverted clock cancels most of it.

   • Lesson E8.2Sample and Hold: The Switch, Charge Injection and kT/C
   • Problem E8.2.1The Pedestal That Came with a Wider Switch
7. Prove ItSolve E8.2.1: The Pedestal That Came with a Wider SwitchSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem E8.2.1