Defending an Analog Block You Designed

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompareScale It

1. Defending an Analog Block You Designed
2. Break ItA Post-Layout SurpriseL2 Mid-LevelL3 Senior

   Tell me about a time your block behaved differently after layout. What changed, and what did you learn?

   Reveal the Model Answer

   A good story names the effect, such as extra parasitic capacitance that cut phase margin or a gradient that added offset. It shows how it was found, by post-layout simulation or measurement, and how it was fixed. It ends with what changed in the method, such as margins kept for parasitics or common-centroid placement planned from the start.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A good story names the effect, such as extra parasitic capacitance that cut phase margin or a gradient that added offset. Key point 2 It shows how it was found, by post-layout simulation or measurement, and how it was fixed. Key point 3 It ends with what changed in the method, such as margins kept for parasitics or common-centroid placement planned from the start.

   • Lesson E7.7What Layout Does About It
   • Lesson E5.7Capstone: A Five-Transistor OTA to Spec
3. CompareHigh vs Low gm/IDL1 JuniorL2 Mid-Level

   Compare biasing a transistor at high g_m/I_D with biasing it at low g_m/I_D.

   Reveal the Model Answer

   High g_m/I_D, near weak inversion, gives the most transconductance per microamp. But the device is wide and slow, and its threshold mismatch becomes a larger current error. Low g_m/I_D, strong inversion, costs current but gives small, fast devices and better current matching. Input pairs often sit high for noise and offset; mirrors and fast stages sit lower.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 High g_m/I_D, near weak inversion, gives the most transconductance per microamp. Key point 2 But the device is wide and slow, and its threshold mismatch becomes a larger current error. Key point 3 Low g_m/I_D, strong inversion, costs current but gives small, fast devices and better current matching. Key point 4 Input pairs often sit high for noise and offset; mirrors and fast stages sit lower.

   • Lesson E2.5Transconductance and gm/ID
   • Lesson E7.4Mismatch and Pelgrom's Law
4. Scale ItReviewing an Analog Block Before Tape-OutL3 SeniorL4 Staff

   You review a colleague's op-amp and bias block a month before tape-out. What evidence do you ask for before you accept it?

   Reveal the Model Answer

   Ask for every specification line with its measured margin at every corner, crossed with supply and temperature. Ask for Monte Carlo mean plus or minus 3σ on offset and matching. Check stability at the worst load and feedback factor, with a step as well as a margin. Check start-up with supply ramps, fast and cold-slow. Finally, ask which known faults the benches were shown to catch.

   1. Dynamic faults

      No R_z and a starved bias leave the settled DC levels right, so only the settling lines catch them for sure.

   Read the diagram as text

   • Your bench: stimulus and meas lines
   • Final design
   • No Rz: phase margin
   • Bias 5 µA: slew rate
   • Load mirror 4/2: input range
   • M2 22/2: offset
   • Verdicts: pass, fail × 4

   • Your bench → Final design
   • Your bench → No Rz
   • Your bench → Bias 5 µA
   • Your bench → Load mirror 4/2
   • Your bench → M2 22/2
   • Final design → Verdicts
   • No Rz → Verdicts
   • Bias 5 µA → Verdicts
   • Load mirror 4/2 → Verdicts
   • M2 22/2 → Verdicts

   • sf, 1.8 V, 27 °C
   • sf, 1.62 V, −40 °C

   Read the plot as a table

   Frequency	sf, 1.8 V, 27 °C	sf, 1.62 V, −40 °C
   1 Hz	79.77 dB	60.13 dB
   10 Hz	79.77 dB	60.13 dB
   100 Hz	79.76 dB	60.13 dB
   1 kHz	79.17 dB	60.12 dB
   10 kHz	67.83 dB	59.42 dB
   100 kHz	48.11 dB	47.38 dB
   1 MHz	28.11 dB	27.61 dB
   10 MHz	7.725 dB	7.411 dB
   100 MHz	-18.93 dB	-17 dB
   1 GHz	-49.24 dB	-45.32 dB

   One corner, two conditions. Only the supply and the temperature change, and the loop gain changes with them.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Ask for every specification line with its measured margin at every corner, crossed with supply and temperature. Key point 2 Ask for Monte Carlo mean plus or minus 3σ on offset and matching. Key point 3 Check stability at the worst load and feedback factor, with a step as well as a margin. Key point 4 Check start-up with supply ramps, fast and cold-slow. Key point 5 Finally, ask which known faults the benches were shown to catch.

   What Interviewers Listen For (Senior)

   A good senior answer asks for PVT corners crossed with Monte Carlo, and for stability in the worst case. It also asks for start-up transients and proof that the benches work.

   Missed Corner

   "It meets spec at typical with an ideal bias source."

   An ideal bias source hides the biggest process effect. The real reference current moves with process, supply and temperature, so the corners must use it.

   Source ASIC Point lesson E7.6

   Half-Truth

   "All the DC checks pass, so the benches are good."

   DC-level checks never see a missing R_z or a starved bias. A bench is trusted only after it fails known faults.

   Source ASIC Point lesson E8.4

   Wrong Altitude

   Reviews only the schematic numbers.

   Layout adds gradients and parasitics, and system use adds loads and supply noise. A senior review asks how those were covered.

   • Lesson E7.6Corners and PVT Sign-Off
   • Lesson E8.4Design It, Then Break It: A DAC Output Buffer
   • Lesson E4.7Capstone: A Bias Block to Spec
   • Lesson E6.6Capstone: Compensate a Two-Stage Op-Amp
   • Problem E7.6.1Nine Settings, One Verdict
   • Problem E8.4.1Break the DAC Buffer
5. WhyWhy a Bench Must Fail Known FaultsL2 Mid-LevelL3 Senior

   Why should a test bench be shown to fail on purpose before you trust it?

   Reveal the Model Answer

   A bench that passes everything may not be measuring what you think. Insert known faults, such as a missing R_z, a starved bias or a swapped input. A good bench fails each one with a clear reason. In the lesson, DC-level checks missed both a missing R_z and a starved bias.

   • final design
   • no R_z
   • bias 5 µA

   1. Time 370 nsfinal design = 61.54 µV · no R_z = 17.13 mV · bias 5 µA = 164.3 mV

      70 ns after the fall only the final design has settled for good. Without R_z the output rings until 112.3 ns; the starved copy slews until 176.1 ns.

   Read the plot as a table

   Time	final design	no R_z	bias 5 µA
   0 s	50.28 µV	50.28 µV	93.29 µV
   100 ns	50.28 µV	50.28 µV	93.29 µV
   200 ns	215.5 µV	-3.915 mV	-29.01 mV
   300 ns	789.4 µV	819.1 µV	-6.087 mV
   370 ns	61.54 µV	17.13 mV	164.3 mV
   400 ns	51.91 µV	2.84 mV	34.21 mV
   500 ns	-1.362 mV	-1.29 mV	5.276 mV
   600 ns	96.08 µV	-1.484 mV	22.49 mV
   700 ns	75.11 µV	110.3 µV	902.4 µV
   800 ns	96.97 µV	155.3 µV	108.6 µV
   900 ns	96.97 µV	96.41 µV	129.2 µV

   Measured on ngspice 42; clipped at ±20 mV.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A bench that passes everything may not be measuring what you think. Key point 2 Insert known faults, such as a missing R_z, a starved bias or a swapped input. Key point 3 A good bench fails each one with a clear reason. Key point 4 In the lesson, DC-level checks missed both a missing R_z and a starved bias.

   • Lesson E8.4Design It, Then Break It: A DAC Output Buffer
   • Problem E8.4.1Break the DAC Buffer
6. Prove ItSolve E8.4.1: Break the DAC BufferSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem E8.4.1

7. What IfChoosing the Faults to Plant in a BenchL2 Mid-LevelL3 Senior

   Which faults would you plant in a DAC output buffer bench, and which check should catch each one?

   Reveal the Model Answer

   Plant faults that a weak bench would miss. Remove R_z: the step settling check at speed must show ringing. Starve the bias: the input-range check at speed must fail near the top code. Swap the inputs: the open-loop sign check must fail. Each check that never fails is measuring nothing useful.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Plant faults that a weak bench would miss. Key point 2 Remove R_z: the step settling check at speed must show ringing. Key point 3 Starve the bias: the input-range check at speed must fail near the top code. Key point 4 Swap the inputs: the open-loop sign check must fail. Key point 5 Each check that never fails is measuring nothing useful.

   Tool as Truth

   "The DC sweeps pass with every fault, so the faults are harmless."

   DC checks cannot see stability or slew. In the lesson they missed both a missing R_z and a starved bias.

   Source Lesson E8.4 key points

   • Lesson E8.4Design It, Then Break It: A DAC Output Buffer
   • Lesson E5.3The Five-Transistor OTA
   • Problem E8.4.1Break the DAC Buffer
8. CompareProcess Corners vs Monte CarloL1 JuniorL2 Mid-Level

   Compare process corners with a mismatch Monte Carlo run. Do you need both?

   Reveal the Model Answer

   Yes. A process corner moves every transistor of a type together, the global spread between wafers. Mismatch moves each transistor alone, the local spread on one die. Offset comes mostly from mismatch, while bias currents and speed move mostly with corners. Sign-off runs corners crossed with supply and temperature, plus Monte Carlo.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Yes. Key point 2 A process corner moves every transistor of a type together, the global spread between wafers. Key point 3 Mismatch moves each transistor alone, the local spread on one die. Key point 4 Offset comes mostly from mismatch, while bias currents and speed move mostly with corners. Key point 5 Sign-off runs corners crossed with supply and temperature, plus Monte Carlo.

   • Lesson E7.6Corners and PVT Sign-Off
   • Lesson E2.7Corners and Temperature
   • Problem E7.6.1Nine Settings, One Verdict
9. Prove ItSolve E7.6.1: Nine Settings, One VerdictSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem E7.6.1

10. Scale ItWriting a Bias Block SpecificationL3 Senior

    You must hand over a bias block to other designers. How do you write its specification and prove it?

    Reveal the Model Answer

    Write each requirement as one line with a limit and a measurement, set after measuring a reference design at every corner. Use one bench per check. Run a supply sweep and a temperature and supply sweep for the worst case. Add an output sweep for compliance and power-up transients, fast and slow. A constant-g_m reference moves its current on purpose, so specify the tail current as a band.

    1. Reference and start-up

       The beta multiplier of E4.4 sets 10 µA with a res_high_po resistor (W = 0.35 µm, L = 8.54 µm). The start-up of E4.5 kicks it on at power-up and then switches off.

    2. Send currents

       PMOS devices on the reference's gate line b copy its current: 10 µA for the NMOS reference stack and 2.5 µA for the cascode bias. Currents travel; gate voltages stay local (E4.2).

    3. Wide-swing cascode

       The 2.5 µA diode XBC sets the cascode gate c. The reference stack sets the bottom gate g with its own cascode, so both bottom devices see the same drain voltage (E4.3). The tail is two units of the stack: 20 µA.

    4. PMOS bias output

       One more unit on gate g sinks 10 µA from a diode-connected 8/1 PMOS. Its gate is pbias: any 8/1 PMOS with its source at VDD and this gate voltage sources about 10 µA.

    Read the diagram as text

    • Start-up: XS1-XS3: kick at power-up, then off
    • Reference: Beta multiplier, K = 4, RS a res_high_po: 10 µA
    • PMOS copies: XP3 4/1: 10 µA; XP4 1/1: 2.5 µA
    • Cascode bias: XBC 0.5/1.5 diode sets node c
    • Reference stack: XC1 over XB1, 16/1 units: node g
    • Tail output: XC2 over XB2, two units: 20 µA
    • PMOS bias output: XB3 sinks 10 µA from XPB 8/1

    • Start-up → Reference: kick
    • Reference → PMOS copies: gate b
    • PMOS copies → Cascode bias: 2.5 µA
    • PMOS copies → Reference stack: 10 µA
    • Cascode bias → Tail output: gate c
    • Reference stack → Tail output: gate g
    • Reference stack → PMOS bias output: gate g

    The full netlist is the Try it below. Units are whole devices (m=2 for the tail), so the 2:1 ratio does not depend on drawn widths matching.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 Write each requirement as one line with a limit and a measurement, set after measuring a reference design at every corner. Key point 2 Use one bench per check. Key point 3 Run a supply sweep and a temperature and supply sweep for the worst case. Key point 4 Add an output sweep for compliance and power-up transients, fast and slow. Key point 5 A constant-g_m reference moves its current on purpose, so specify the tail current as a band.

    • Lesson E4.7Capstone: A Bias Block to Spec
    • Problem E4.7.1Catch the Bad Bias Block
11. What IfA DAC Buffer's Input Range at the CornersL2 Mid-LevelL3 Senior

    Asked if the block drives a DAC or ADC

    What if a DAC output buffer passes at typical but a corner moves its input range?

    Reveal the Model Answer

    A corner can push an edge of the input range past the top or bottom code. Then the buffer's tail leaves saturation at that code and the output error jumps. Choose the DAC references inside the buffer's range at speed, not just where the DC error is small. Check them at every corner.

    • version 2
    • version 3

    Read the plot as a table

    Input	version 2	version 3
    700 mV	-149.8 µV	-88.19 µV
    800 mV	13.66 µV	37.73 µV
    900 mV	48.87 µV	64.35 µV
    1 V	93.74 µV	89.88 µV
    1.1 V	630.6 µV	211.5 µV
    1.2 V	10.28 mV	2.951 mV
    1.3 V	47.59 mV	33.11 mV

    DC error at the sf corner and -40 °C. At the top code, version 2 errs by 9.02 mV and version 3 by 2.42 mV.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 A corner can push an edge of the input range past the top or bottom code. Key point 2 Then the buffer's tail leaves saturation at that code and the output error jumps. Key point 3 Choose the DAC references inside the buffer's range at speed, not just where the DC error is small. Key point 4 Check them at every corner.

    • Lesson E8.4Design It, Then Break It: A DAC Output Buffer
    • Lesson E8.3A DAC: The R-2R Ladder and Its Linearity
    • Problem E8.4.1Break the DAC Buffer
    • Problem E8.3.1Linear on the Least Switch Area