A Priority Encoder with Wildcard Case Items

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WhyWhat IfProve ItCompareScale It

1. A Priority Encoder with Wildcard Case Items
2. WhyWhy Casex Matches an Unknown InputL2 Mid-Level

   Why does casex match x001 against 4'b1???? And what does this casez version print for a floating top bit?

   module prienc4 (input logic [3:0] req, output logic [1:0] idx, output logic valid);
     always_comb begin
       idx = 2'd0; valid = 1'b1;
       casez (req)
         4'b1???: idx = 2'd3;      // the highest set bit wins
         4'b01??: idx = 2'd2;
         4'b001?: idx = 2'd1;
         4'b0001: idx = 2'd0;
         default: valid = 1'b0;    // no request
       endcase
     end
   endmodule
   module tb;
     logic [3:0] req; logic [1:0] idx; logic valid;
     prienc4 dut (.req(req), .idx(idx), .valid(valid));
     initial begin
       req = 4'bz001; #1;      // the top request line is left floating
       $display("req=z001: idx=%0d valid=%b", idx, valid);
     end
   endmodule
   

   Reveal the Model Answer

   Wildcard case statements mask bits on both sides of the comparison. casex ignores X and Z wherever they appear, so the X in req matches the 1. casez does the same for Z, so z001 matches 1??? and this prints idx=3. In silicon the floating line is a real 0 or 1, so the gates may do something else.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: req=z001: idx=3 valid=1

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Wildcard case statements mask bits on both sides of the comparison. Key point 2 casex ignores X and Z wherever they appear, so the X in req matches the 1. Key point 3 casez does the same for Z, so z001 matches 1??? and this prints idx=3. Key point 4 In silicon the floating line is a real 0 or 1, so the gates may do something else.

   Misconception

   "Wildcards apply only to the bits written as ? in the items."

   That is the rule for case inside. In casex and casez, unknown bits in the case expression are wildcards too.

   Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. appendix C.3.3 Casex, casez and case...inside statements

   • Lesson R1.5Case Statements: Priority, Parallel, Unique
3. CompareCase Inside vs CasezL2 Mid-Level

   Compare case inside with casez for the same encoder.

   Reveal the Model Answer

   case inside compares with the wildcard equality operator, so only X, Z or ? bits in the items are masked. An unknown bit in req then fails every item and falls to default. It synthesizes to the same 5 cells as the casez version on this flow. Icarus 12 does not parse case inside, so check your tools first.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 case inside compares with the wildcard equality operator, so only X, Z or ? bits in the items are masked. Key point 2 An unknown bit in req then fails every item and falls to default. Key point 3 It synthesizes to the same 5 cells as the casez version on this flow. Key point 4 Icarus 12 does not parse case inside, so check your tools first.

   Misconception

   "case inside is not synthesizable."

   Synthesis supports it. On this site's flow the case inside encoder gives the same 5 cells and 2 levels as casez.

   Source Measured: the encoder rewritten with case inside, Yosys 0.70+290 (OSS CAD Suite 2026-11-02), slang front end, synth -flatten with ABC, ltp -noff

   Tool as Truth

   "Our simulator rejected case inside, so the standard does not have it."

   It is in the standard. Icarus 12 reports a syntax error on it, while Verilator 5.052 and the synthesis front end accept it.

   Source Measured: case inside compiled on each tool, Icarus Verilog 12; Verilator 5.052; Yosys 0.70+290 (OSS CAD Suite 2026-11-02), slang front end, synth -flatten with ABC, ltp -noff

   • Lesson R1.5Case Statements: Priority, Parallel, Unique
4. What IfA Priority Encoder for Any WidthL2 Mid-Level

   Asked if the request bus is wide or parameterized

   What if the request bus is 16 bits, or a parameter? Write the encoder without listing every item.

   Reveal the Model Answer

   Use a for loop that walks from bit 0 up and overwrites idx on every set bit. The last write wins, so the highest set bit wins. Set the defaults before the loop. Synthesis unrolls the loop into a chain. On this flow the 16-bit version is 40 cells and 12 levels, so depth grows with width.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: 65536 request patterns, 0 wrong

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Use a for loop that walks from bit 0 up and overwrites idx on every set bit. Key point 2 The last write wins, so the highest set bit wins. Key point 3 Set the defaults before the loop. Key point 4 Synthesis unrolls the loop into a chain. Key point 5 On this flow the 16-bit version is 40 cells and 12 levels, so depth grows with width.

   Misconception

   "A loop in RTL runs over several clock cycles."

   A synthesizable loop is unrolled into logic that settles in one cycle. Its depth is what costs you.

   Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 6.3 Looping statements

   • Lesson R1.7Parameters, Generate and $clog2
   • Lesson R5.4Round-Robin and Priority Arbiters
5. Scale ItCutting the Depth of a Wide Priority EncoderL2 Mid-LevelL3 Senior

   The 16-bit encoder is too deep for your clock. Restructure it.

   Reveal the Model Answer

   Split the bus into four groups of four. Each group has a small encoder and a "busy" bit. A top encoder picks the highest busy group, and its number forms the upper bits of idx. The run proves the two versions equal on all inputs. On this flow the grouped one has 8 levels instead of 12, for about the same cells.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: 65536 requests: 0 differences between the loop and the grouped encoder

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Split the bus into four groups of four. Key point 2 Each group has a small encoder and a "busy" bit. Key point 3 A top encoder picks the highest busy group, and its number forms the upper bits of idx. Key point 4 The run proves the two versions equal on all inputs. Key point 5 On this flow the grouped one has 8 levels instead of 12, for about the same cells.

   What Interviewers Listen For (Senior)

   A good senior answer proves the restructured encoder equal to the original before measuring it. It also says when to stop restructuring and add a pipeline stage instead.

   Half-Truth

   "Synthesis will find the tree on its own."

   Sometimes it does, often it does not: on this flow the loop stayed at 12 levels. Measure, and restructure the RTL when the report says so.

   Source Measured: the loop and grouped encoders, Yosys 0.70+290 (OSS CAD Suite 2026-11-02), slang front end, synth -flatten with ABC, ltp -noff

   • Lesson R4.1Clock Period, Setup and Hold in One Picture
   • Lesson R5.4Round-Robin and Priority Arbiters
6. Prove ItSolve R1.5.1: A Priority Encoder with a Collision FlagSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem R1.5.1