Why ASICs Avoid Clocks Made in Logic

Where the interviewer goes next. Open a node to practise that follow-up.

WhyBreak ItCompareScale It

1. Why ASICs Avoid Clocks Made in Logic
2. WhyWhy STA Must Be Told About a Generated ClockL2 Mid-Level

   Why can't STA simply time the flops behind a divider without a new constraint?

   Reveal the Model Answer

   STA times paths from clocks it knows. A divider's output is a flop output, so STA does not treat it as a clock unless told. create_generated_clock names it, gives its ratio to the master and lets the tool add the divider delay to the clock latency.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 STA times paths from clocks it knows. Key point 2 A divider's output is a flop output, so STA does not treat it as a clock unless told. Key point 3 create_generated_clock names it, gives its ratio to the master and lets the tool add the divider delay to the clock latency.

   Tool as Truth

   Puts a second create_clock directly on the divider output.

   That makes an unrelated clock that starts at the divider, so the divider's own delay is lost. L2.6 measured a clock latency of 0 that way.

   Source Lesson L2.6, measured with OpenROAD (OpenSTA 3.1.0) on sky130hd, 2026-11-03

3. CompareA Clock Enable Instead of a Divided ClockL1 JuniorL2 Mid-Level

   Compare running slow logic on a divided clock with running it on the main clock and an enable.

   Reveal the Model Answer

   With an enable, the logic keeps the main clock and updates only when a one-cycle tick is high. There is one clock tree, no crossing, and STA times it normally. The cost is the enable logic and some clock power. Clock gating with a library cell can remove most of that power.

   1. clk low

      The latch is open: a new en passes to the AND gate. The AND output is 0, because clk is 0.

      Follow the calls, values and waits

      1. data en: en → Latch
      2. data en: Latch → AND gate
   2. clk high

      The latch is closed. A change on en stops at the latch, so gclk is either a whole clock pulse or nothing.

   Read the diagram as text

   • en: from a flop
   • clk: free-running
   • Latch: open while clk is low
   • AND gate: clk & held en
   • gclk: whole pulses only

   • en → Latch: en
   • Latch → AND gate: held en
   • clk → AND gate: clk
   • AND gate → gclk

   A latch-and-AND model of this cell, run on the lab bench, writes 11 22 33 44: no extra entries.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 With an enable, the logic keeps the main clock and updates only when a one-cycle tick is high. Key point 2 There is one clock tree, no crossing, and STA times it normally. Key point 3 The cost is the enable logic and some clock power. Key point 4 Clock gating with a library cell can remove most of that power.

   Missed Corner

   "An enable makes the slow logic's paths run at the slow rate in STA."

   STA still times them for one fast period unless you add a multicycle path. That is safe only when the enable really guarantees it.

   Source OpenSTA 3.1.0 command reference, set_multicycle_path (as cited in lesson L2.8)

   • Lesson R2.3Enables and Gated Clocks
   • Lesson L2.8False Paths and Multicycle Paths
4. Scale ItWho Makes the Clocks on an SoCL3 SeniorL4 Staff

   Scale it: on an SoC with many blocks, who should make the clocks, and what should block RTL contain?

   Reveal the Model Answer

   A clock controller makes the clocks: PLLs, dividers, glitch-free switches and gating cells taken from the library. It ships with its constraints. Block RTL receives clocks and uses enables or library gating cells. It never builds clocks from its own logic. Then STA, clock-tree synthesis and CDC checks all start from one list of clocks.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A clock controller makes the clocks: PLLs, dividers, glitch-free switches and gating cells taken from the library. Key point 2 It ships with its constraints. Key point 3 Block RTL receives clocks and uses enables or library gating cells. Key point 4 It never builds clocks from its own logic. Key point 5 Then STA, clock-tree synthesis and CDC checks all start from one list of clocks.

   Wrong Altitude

   Each block team writes its own divider "to save a request to the clock team".

   Each one is an undeclared domain with its own skew and its own crossings. The chip-level constraints and CDC analysis then miss them.

   Half-Truth

   Writes the clock-gating latch and AND in RTL.

   The library ICG cell carries the timing checks on its enable pin that STA needs. A hand-made latch and AND does not carry them.

   Source SkyWater sky130_fd_sc_hd Liberty, cells dlclkp_1 and sdlclkp_1 (as read for lesson L5.6)

   • Lesson L5.6Clock Gating Cells in the Tree
   • Lesson L2.6Clocks in SDC
5. Break ItSwitching to a Clock That Is Not RunningL2 Mid-LevelL3 Senior

   Asked if they offer the glitch-free switch

   Break it: what happens if the glitch-free switch selects a clock that is stopped?

   Reveal the Model Answer

   The old side turns off on its own falling edge. The new side turns on only at a falling edge of the new clock. If that clock is stopped, it never turns on, so the output stays low. The system must start the new clock first, or use a switch with a fallback.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The old side turns off on its own falling edge. Key point 2 The new side turns on only at a falling edge of the new clock. Key point 3 If that clock is stopped, it never turns on, so the output stays low. Key point 4 The system must start the new clock first, or use a switch with a fallback.

   Missed Corner

   "A glitch-free switch always completes."

   Its handover needs edges from both clocks. The twin switches to a stopped clock and counts no output edges after the switch.

   Run It

   The glitch-free switch with clk_b held at 0.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: rising edges on clk_out after the switch: 0 FAIL: switching to a stopped clock leaves no clock at all; the handover needs edges from both clocks

   See the Fix

   `timescale 1ns/1ps
   module tb;
     logic clk_a = 0, clk_b = 0, sel = 0, clk_out;
     always #5 clk_a = ~clk_a;                    // 10 ns clock
     always #8 clk_b = ~clk_b;                    // 16 ns clock
     // Glitch-free switch (simplified: real designs add synchronizer flops on sel in each domain).
     // Each side turns off on its own falling edge, and the other side waits until it is off.
     logic qa = 1, qb = 0;
     always @(negedge clk_a) qa <= ~sel & ~qb;
     always @(negedge clk_b) qb <=  sel & ~qa;
     assign clk_out = (clk_a & qa) | (clk_b & qb);
     realtime t_last = 0, min_hi = 1000, min_lo = 1000;
     int edges_after = 0;
     always @(clk_out) begin
       if ($realtime > 0 && clk_out === 0 && $realtime - t_last < min_hi) min_hi = $realtime - t_last;
       if ($realtime > 0 && clk_out === 1 && $realtime - t_last < min_lo) min_lo = $realtime - t_last;
       t_last = $realtime;
       if ($realtime > 60 && clk_out === 1) edges_after++;
     end
     initial begin
       #17 sel = 1;                               // switch while clk_a is high and clk_b is low
       #180;
       $display("rising edges on clk_out after the switch: %0d", edges_after);
       if (edges_after > 0) $display("PASS: with both clocks running the switch completes");
       $finish;
     end
   endmodule
   

   Prints: PASS: with both clocks running the switch completes