A Blocking Temporary Inside Always_ff

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WhyWhat IfBreak ItCompare

1. A Blocking Temporary Inside Always_ff
2. WhyWhy Blocking Is Allowed in Always_ffL2 Mid-Level

   If blocking writes cause so many bugs in clocked blocks, why does the language allow them in always_ff?

   Reveal the Model Answer

   Some clocked blocks need an intermediate value inside the same edge, such as a temporary or a loop variable. A blocking write gives that value at once. The rules for always_ff limit timing controls and other writers. They do not ban =, so lint is where the house rule gets enforced.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Some clocked blocks need an intermediate value inside the same edge, such as a temporary or a loop variable. Key point 2 A blocking write gives that value at once. Key point 3 The rules for always_ff limit timing controls and other writers. Key point 4 They do not ban =, so lint is where the house rule gets enforced.

   Misconception

   "always_ff turns = into <= for you."

   It changes nothing about how assignments behave. A blocking write in always_ff still updates at once, as the shift-register question shows.

   Source IEEE 1800-2017 §9.2.2.4

   • Lesson R2.1always_ff, Old State and Next State
3. What IfAnother Block Reads the TemporaryL2 Mid-Level

   What if a second always_ff block reads sum at the same clock edge?

   Reveal the Model Answer

   Then the two blocks race. sum changes in the Active region at the edge, and the reader runs in the same region in either order. It may get this edge's sum or the last one. Declare the temporary inside the block, so nothing outside can read it.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Then the two blocks race. Key point 2 sum changes in the Active region at the edge, and the reader runs in the same region in either order. Key point 3 It may get this edge's sum or the last one. Key point 4 Declare the temporary inside the block, so nothing outside can read it.

   Missed Corner

   "It is fine because sum is just a wire in the netlist."

   The netlist is not the problem; the simulation is. Your RTL tests could pass with one order and hide a bug the gates do not have.

   Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 8.1.4.3 Using blocking assignments for temporary variables (note)

   • Lesson R2.1always_ff, Old State and Next State
4. What IfWhen Two Simulators Agree on a RaceL2 Mid-LevelL3 Senior

   What if Icarus and Verilator give the same result for that race? Is the code safe then?

   Reveal the Model Answer

   No. The standard lets the two blocks run in either order inside the Active region. Two tools agreeing only means they chose the same order today. A new version, an extra block or a different file order can change it. Lint for a blocking variable read outside its block, and declare the temporary locally.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No. Key point 2 The standard lets the two blocks run in either order inside the Active region. Key point 3 Two tools agreeing only means they chose the same order today. Key point 4 A new version, an extra block or a different file order can change it. Key point 5 Lint for a blocking variable read outside its block, and declare the temporary locally.

   Tool as Truth

   "Both simulators agree, so the order is fixed."

   The standard leaves the order open. Tools agree because of how they happen to be built, and any edit can change that.

   Source IEEE 1800-2017 §4.7

   • Lesson R2.3Enables and Gated Clocks
5. CompareAn Inline Temporary vs a Separate Combinational BlockL2 Mid-Level

   Compare the inline temporary with computing sum in its own always_comb block.

   Reveal the Model Answer

   Both give the same hardware. A separate always_comb keeps each block to one kind of assignment, so lint rules stay simple. It also makes sum visible in waveforms. The inline form keeps the logic in one place but mixes = and <=. Many style guides choose the separate block for that reason.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Both give the same hardware. Key point 2 A separate always_comb keeps each block to one kind of assignment, so lint rules stay simple. Key point 3 It also makes sum visible in waveforms. Key point 4 The inline form keeps the logic in one place but mixes = and <=. Key point 5 Many style guides choose the separate block for that reason.

   Misconception

   "The separate block adds a register stage."

   always_comb describes logic with no memory. The sum still reaches the flop in the same cycle.

   Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 7.2 The always and always_comb procedures

   • Lesson R2.1always_ff, Old State and Next State
   • Lesson R7.3Coding for Review and Debug
6. Break ItA Temporary Written on Only One PathL2 Mid-LevelL3 Senior

   How would you break the temporary? Suppose sum is written only under if (en). What does this print, and what does synthesis build?

   module avg2e (input logic clk, en, input logic [7:0] a, b, output logic [7:0] avg);
     logic [8:0] sum;
     always_ff @(posedge clk) begin
       if (en) sum = a + b;      // written only when en is 1
       avg <= sum[8:1];
     end
   endmodule
   module tb;
     logic clk = 0, en = 1; logic [7:0] a = 10, b = 20, avg;
     avg2e dut (.clk(clk), .en(en), .a(a), .b(b), .avg(avg));
     always #5 clk = ~clk;
     initial begin
       @(posedge clk); #1 en = 0; a = 100; b = 100;
       @(posedge clk); #1;
       $display("en=0, a=b=100: avg=%0d", avg);
       $finish;
     end
   endmodule
   

   Reveal the Model Answer

   When en is 0, sum keeps the value from the last enabled edge, so it is memory now. The run prints avg=15, from the old inputs. On this flow Yosys did not add 9 flops for sum. It folded the memory into an enable on the 8 avg flops. Another tool may build it differently, so read the report.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: en=0, a=b=100: avg=15

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 When en is 0, sum keeps the value from the last enabled edge, so it is memory now. Key point 2 The run prints avg=15, from the old inputs. Key point 3 On this flow Yosys did not add 9 flops for sum. Key point 4 It folded the memory into an enable on the 8 avg flops. Key point 5 Another tool may build it differently, so read the report.

   Misconception

   "A blocking temporary is always a wire."

   Only when every path writes it before reading it. Here the en = 0 path reads the old value, which needs storage.

   Source Measured: the run on this question, Icarus Verilog 12

   • Lesson R2.1always_ff, Old State and Next State