Interview Question · Waveform
Why a Clock Gate Needs a Latch
The Question
The interviewer asks
A designer gates a clock with assign gclk = clk & en_q;, where en_q comes from a flop on clk. Draw what goes wrong, and fix it.
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Reveal the Model Answer
The flop changes en_q just after the rising edge, while clk is still high. So the AND output rises in the middle of a high phase, and the gated flops see an extra edge. A clock-gating cell puts a latch in front of the AND. The latch is open while clk is low and holds while it is high. So the enable can only change the gated clock between pulses.
Columns are half periods from t = 10 to 40. At t = 15, en_q rises while clk is high, and the AND passes an edge the enable never asked for. The ICG passes only t = 25 and t = 35.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer draws clk, en_q and the AND output on one timeline. It points at the high phase where the enable changes.
What Interviewers Listen For (Senior)
A good senior answer uses the library ICG cell instead of a hand-made latch, so STA checks the enable. It also asks how the gate is forced on during scan test.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompareScale It
- Why a Clock Gate Needs a Latch
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WhyWhy the ICG Latch Is Open While the Clock Is LowL1 JuniorL2 Mid-Level
Why is the latch open while the clock is low, and not while it is high?
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Reveal the Model Answer
While the clock is low, the AND output is 0 whatever the enable does. So the enable may change freely then. When the clock rises, the latch closes and holds the enable for the whole high phase. The gated clock then shows either a full pulse or none.
Inside a Clock-Gating CellArrows show signals. The latch passes en only while clk is low. Illustrative sequenceCallValueReturnWaiting- clk low
The latch is open: a new
enpasses to the AND gate. The AND output is 0, becauseclkis 0.Follow the calls, values and waits
- data en: en → Latch
- data en: Latch → AND gate
- clk high
The latch is closed. A change on
enstops at the latch, sogclkis either a whole clock pulse or nothing.
Read the diagram as text
- en: from a flop
- clk: free-running
- Latch: open while clk is low
- AND gate: clk & held en
- gclk: whole pulses only
- en → Latch: en
- Latch → AND gate: held en
- clk → AND gate: clk
- AND gate → gclk
A latch-and-AND model of this cell, run on the lab bench, writes 11 22 33 44: no extra entries.
Self-Check
Tick each key point you covered in your answer.
Misconception
"A latch open while the clock is high works the same way."
Then the enable passes straight to the AND during the high phase, which is exactly when it must not change.
Source SkyWater sky130_fd_sc_hd Liberty, cells dlclkp_1 and sdlclkp_1 (as read for lesson L5.6)
- clk low
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CompareThe Library ICG Cell vs a Latch and an AND in RTLL2 Mid-Level
Compare writing the latch and AND in RTL with using the library clock-gating cell.
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Reveal the Model Answer
The library cell carries setup and hold checks on its enable pin, so STA checks the enable against the clock. Clock-tree tools also know it is a gate in the clock path. Loose gates get none of that. Synthesis can insert the cell for you from ordinary enables, if the flow has a gating step and a library.
Self-Check
Tick each key point you covered in your answer.
Tool as Truth
"Synthesis always turns enables into clock gates."
It needs a gating step and a library ICG cell. The Yosys flow on this site has neither, so it builds enabled flops.
Source Yosys 0.70 command reference, help clockgate (as read for lesson R2.3)
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Scale ItWhere to Put the Clock GatesL3 Senior
Scale it: on a large block, do you put one gate at the clock root? Or many small ones near the registers?
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Reveal the Model Answer
A gate near the root stops the most clock tree when the whole block is idle, but only then. Small gates near registers catch more idle cycles, but each costs a cell and timing on its enable. Decide from measured activity: which groups are idle together, and how often. Check the result with power analysis on realistic traffic.
Two ICGs in One TreeArrows are the clock, except en, the enable fromef. Both ICGs check the sameen.Illustrative sequence- Near the root
icg_rootsees the edge at 0.1440 ns,efat 0.4562 ns: skew -0.3122 ns. - Near the leaves
icg_leafshares two buffers withefand sees the edge at 0.3560 ns: skew -0.1002 ns.
Read the diagram as text
- root clkbuf_4: after the port
- icg_root: CLK at the root
- ub1 → ub2: two buffers
- icg_leaf: CLK one level up
- ub3 → ef: launches en
- fa0, fa1: behind 3 buffers
- fb0, fb1: behind 1 buffer
- root clkbuf_4 → icg_root: CLK
- root clkbuf_4 → ub1 → ub2: clock
- ub1 → ub2 → icg_leaf: CLK
- ub1 → ub2 → ub3 → ef: clock
- icg_root → fa0, fa1: GCLK
- icg_leaf → fb0, fb1: GCLK
- ub3 → ef → icg_leaf: en
Latencies from the two paths below. Closer to the root gates more of the tree, and costs the enable more time.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"More gates always save more power."
Each gate adds a cell, its own clock load and an enable path to time. Gating a bank that is rarely idle can cost more than it saves.
Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 9.2 Dynamic low-power verification challenges (power depends on the use case)
- Near the root
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What IfClock Gates During Scan TestL2 Mid-Level
Asked if they mention test or DFT
What happens to a gated register during scan test, when the functional enable is not driven?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
In scan mode the flops must shift on every clock, whatever the functional enable says. So the scan version of the ICG cell has an extra scan-enable input, ORed with the enable. Test logic holds it high, so the gated clock runs.
Self-Check
Tick each key point you covered in your answer.
Missed Corner
"Scan test does not go through the clock gates."
The gated flops get their clock only through the gate. Without a scan enable on it, they would not shift.
Source SkyWater sky130_fd_sc_hd Liberty, cells dlclkp_1 and sdlclkp_1 (as read for lesson L5.6)
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Prove ItSolve R2.3.1: The Accumulator That Added TwiceSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"An AND gate gates a clock; the enable comes from a clean flop, so there is no glitch."
A flop on the same clock changes its output just after the rising edge, while the clock is high. The twin counts three edges for a two-cycle enable.
Run It
The enable is high for two cycles; edges of the AND-gated clock are counted.
gated edge at t=15 enable high for 2 cycles: 3 gated edges FAIL: the AND passed an extra edge when en_q rose while clk was highSee the Fix
module tb;
logic clk = 0, en = 0, en_q = 0, gclk;
int edges = 0;
always #5 clk = ~clk;
always_ff @(posedge clk) en_q <= en; // the enable comes from a flop on the same clock
// ICG model: a latch, open while clk is low, in front of the AND.
logic en_l;
always_latch if (!clk) en_l = en_q;
assign gclk = clk & en_l;
always @(posedge gclk) begin edges++; $display("gated edge at t=%0t", $time); end
initial begin
@(negedge clk) en = 1; // ask for two gated edges
@(negedge clk);
@(negedge clk) en = 0;
repeat (3) @(negedge clk);
$display("enable high for 2 cycles: %0d gated edges", edges);
if (edges == 2) $display("PASS: the latch holds the enable while clk is high, so only the two wanted edges pass");
$finish;
end
endmodule
Prints: gated edge at t=25 gated edge at t=35 enable high for 2 cycles: 2 gated edges PASS: the latch holds the enable while clk is high, so only the two wanted edges pass
Half-Truth
"Use a flop on the falling edge instead of the latch, it is the same."
It stops the glitch too, but it samples the enable half a cycle earlier. The library cell is a latch, and STA knows its checks.
Source SkyWater sky130_fd_sc_hd Liberty, cells dlclkp_1 and sdlclkp_1 (as read for lesson L5.6)
Buzzword Without Mechanism
Says "use an ICG" without saying what is inside it.
The interviewer wants the mechanism: a latch transparent while the clock is low, then an AND.