Choosing a Low-Power Strategy

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfBreak ItCompareScale It

1. Choosing a Low-Power Strategy
2. WhyPower Gating vs Stopping the ClockL2 Mid-LevelL3 Senior

   Why switch a domain's power off, when stopping its clock already stops the switching?

   Reveal the Model Answer

   Stopping the clock removes dynamic power only. Transistors still leak while the supply is on. In small process nodes, leakage can be a large part of the total. Only removing the supply removes it, at the cost of losing state and a wake-up time.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Stopping the clock removes dynamic power only. Key point 2 Transistors still leak while the supply is on. Key point 3 In small process nodes, leakage can be a large part of the total. Key point 4 Only removing the supply removes it, at the cost of losing state and a wake-up time.

   Misconception

   "Clock gating removes all power of an idle block."

   It removes switching power. Leakage continues as long as the block is powered.

   Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 9.1 Power requirements (static power and power gating)

3. What IfThe Order of Isolation, Save and Power-OffL2 Mid-LevelL3 Senior

   What if the isolation is turned on a cycle after the power goes off?

   Reveal the Model Answer

   For that cycle the domain's outputs are unknown, and always-on logic samples them. Power-down must go in order: isolate, save state into retention, then switch off. Power-up goes the other way: switch on, restore, then release isolation.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 For that cycle the domain's outputs are unknown, and always-on logic samples them. Key point 2 Power-down must go in order: isolate, save state into retention, then switch off. Key point 3 Power-up goes the other way: switch on, restore, then release isolation.

   Missed Corner

   "One cycle late does not matter; the counter only counts pulses."

   Any flop that samples the unknown value in that cycle is corrupted. The twin's counter turns into X.

   Run It

   Power goes off at one falling edge; isolation follows at the next.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: after power-off: events=xx FAIL: isolation one cycle after power-off let an X into the always-on counter

   See the Fix

   module tb;
     logic clk = 0, pwr_on = 1, iso_en = 0;
     logic pd_raw = 0, pd_out, ao_in;
     logic [7:0] events = 0;                       // always-on counter of valid pulses
     always #5 clk = ~clk;
     // The switched domain: its output is unknown while its power is off.
     assign pd_out = pwr_on ? pd_raw : 1'bx;
     assign ao_in = iso_en ? 1'b0 : pd_out;      // isolation cell, clamps to 0
     always_ff @(posedge clk) events <= events + ao_in;
     initial begin
       @(negedge clk) pd_raw = 1;
       @(negedge clk) pd_raw = 0;
       @(negedge clk) pd_raw = 1;
       @(negedge clk) pd_raw = 0;                    // two valid pulses while powered
       @(negedge clk) iso_en = 1;                    // isolate first
       @(negedge clk) pwr_on = 0;                    // then switch the power off
       repeat (3) @(negedge clk);
       $display("after power-off: events=%h", events);
       if (events == 2) $display("PASS: the clamped input kept the always-on counter at 2");
       $finish;
     end
   endmodule
   

   Prints: PASS: the clamped input kept the always-on counter at 2

4. CompareDVFS vs Power GatingL3 Senior

   Compare DVFS with power gating. When would you choose each?

   Reveal the Model Answer

   DVFS keeps the block running at a lower voltage and frequency, so it keeps its state and cuts dynamic power steeply. It suits work that can run slower. Power gating removes leakage completely, but loses state unless retained, and takes time to wake. It suits blocks that sit idle for long periods.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 DVFS keeps the block running at a lower voltage and frequency, so it keeps its state and cuts dynamic power steeply. Key point 2 It suits work that can run slower. Key point 3 Power gating removes leakage completely, but loses state unless retained, and takes time to wake. Key point 4 It suits blocks that sit idle for long periods.

   Half-Truth

   "DVFS only changes the frequency."

   Lowering frequency alone saves power in proportion. Lowering voltage too gives the large saving, and it needs level shifters between domains.

   Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 9.2 Dynamic low-power verification challenges (DVFS)

5. Scale ItVerifying the Power IntentL3 SeniorL4 Staff

   Scale it: how do you verify the power intent of an SoC with many switched domains?

   Reveal the Model Answer

   Write the intent in UPF: domains, supplies, power states, isolation and retention. Run simulation that reads the UPF, so off domains really corrupt their outputs, and test every power-state change. Add structural checks that isolation cells and level shifters sit where the states need them. Then check the netlist with its power cells against the RTL with low-power equivalence.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Write the intent in UPF: domains, supplies, power states, isolation and retention. Key point 2 Run simulation that reads the UPF, so off domains really corrupt their outputs, and test every power-state change. Key point 3 Add structural checks that isolation cells and level shifters sit where the states need them. Key point 4 Then check the netlist with its power cells against the RTL with low-power equivalence.

   Wrong Altitude

   "The UPF is the back-end team's file."

   UPF is read by simulation and structural checks too. Bugs in the power intent are functional bugs, found only if verification reads it.

   Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 10.7 Low power structural checks

6. Break ItThe Register That Forgot Its StateL3 Senior

   Break it: which bug escapes if only plain RTL simulation is run on a power-gated design?

   Reveal the Model Answer

   A register that needs retention but was left out of the retention list. In plain RTL it never loses its value, so wake-up looks perfect. In silicon it comes back random after power-up. Only power-aware simulation, which corrupts non-retained state at power-off, shows it.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A register that needs retention but was left out of the retention list. Key point 2 In plain RTL it never loses its value, so wake-up looks perfect. Key point 3 In silicon it comes back random after power-up. Key point 4 Only power-aware simulation, which corrupts non-retained state at power-off, shows it.

   Half-Truth

   "Retain every register to be safe."

   Retention cells cost area and always-on power. Retain only state that cannot be rebuilt quickly after wake-up.

   Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 9.5.7.2 set_retention_control (retention only where state cannot be restored quickly)