Interview Question · Concept

X Optimism in an If Statement

L1 JuniorL2 Mid-LevelL3 Seniorsimulation synthesis mismatchx propagation

The interviewer asks

The select of an if is X in RTL simulation. What does the output show, and why can that hide a bug?

Reveal the Model Answer

An if whose condition is X takes the else branch. So the output shows a clean value from the else side, and the unknown select disappears. In silicon the select is a real 0 or 1, and nobody knows which. RTL simulation looks fine while the chip may pick either branch. The ternary operator is less optimistic: it gives X wherever the two inputs differ.

One Unreset Flop, Three ReadingsThe same path read by four-state simulation, a two-state simulator and formal. Arrows mean "feeds".

data: where the transaction goes

Read the diagram as text

mode[3:0], no reset: four-state sim: X. Two-state sim: 0. Formal: any value, chosen per run
mode == 4'd3: four-state: X. Two-state: 0. Formal: 1 if the solver chose 3
en = armed && (mode == 3): four-state: X once armed
if (en) in a consumer: four-state: X counts as false, the else branch runs
gate-level simulation: the X spreads through the netlist: pessimism
silicon: the flop powers up 0 or 1 per bit; sometimes 3

mode[3:0], no reset → mode == 4'd3
mode == 4'd3 → en = armed && (mode == 3)
en = armed && (mode == 3) → if (en) in a consumer: optimism
en = armed && (mode == 3) → gate-level simulation
mode[3:0], no reset → silicon

Neither simulation says what the hardware does. Formal has no X: it treats the unknown as a value it may pick, and picks the one that breaks the rule.

The same select, X, into an if and into ?:.

RUNIcarus Verilog · in your browser

Edit the code, then run it

Expected: sel=x: if gives 1010, ?: gives 1xx0

module tb;
  logic sel = 1'bx; logic [3:0] a = 4'b1100, b = 4'b1010, y_if, y_mux;
  always_comb if (sel) y_if = a; else y_if = b;
  always_comb y_mux = sel ? a : b;
  initial #1 $display("sel=x: if gives %b, ?: gives %b", y_if, y_mux);
endmodule

Self-Check

Tick each key point you covered in your answer.

Key point 1 An if whose condition is X takes the else branch. Key point 2 So the output shows a clean value from the else side, and the unknown select disappears. Key point 3 In silicon the select is a real 0 or 1, and nobody knows which. Key point 4 RTL simulation looks fine while the chip may pick either branch. Key point 5 The ternary operator is less optimistic: it gives X wherever the two inputs differ.

What Interviewers Listen For (Junior)

A good junior answer says the else branch runs and the X is lost. It gives a flop without reset as one source of the X.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfCompareScale It

X Optimism in an If Statement
WhyWhy the Language Is X-OptimisticL2 Mid-Level
Why would a language choose to hide X at all?

Reveal the Model Answer

Because pessimism breaks real circuits in simulation. Take a synchronous reset that ANDs the data with an active-low reset. If an X data input made the AND output X, the flop would never reset in simulation. Silicon resets fine, because 0 AND anything is 0. Optimism matches silicon in cases like that and hides bugs in others.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Because pessimism breaks real circuits in simulation. Key point 2 Take a synchronous reset that ANDs the data with an active-low reset. Key point 3 If an X data input made the AND output X, the flop would never reset in simulation. Key point 4 Silicon resets fine, because 0 AND anything is 0. Key point 5 Optimism matches silicon in cases like that and hides bugs in others.

Misconception

"X optimism is a simulator bug."

It is defined behaviour, chosen so common structures such as resets simulate like silicon. The cost is hidden ambiguity elsewhere.

Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. appendix C.3 An optimistic X
- Lesson R2.2Reset: Assert, Release, and What RTL Cannot Show
Scale ItAn X-Propagation Strategy for a BlockL3 SeniorL4 Staff
At the block level, how do you make sure X optimism is not hiding a reset or initialization bug?

Reveal the Model Answer

Reset every control flop, and allow reset-less flops only in the datapath where a valid bit guards them. Add assertions that control signals are never unknown after reset. Run a formal X-propagation check, or gate-level simulation on the boot and reset tests. Some simulators also offer X-propagation modes that make RTL less optimistic.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Reset every control flop, and allow reset-less flops only in the datapath where a valid bit guards them. Key point 2 Add assertions that control signals are never unknown after reset. Key point 3 Run a formal X-propagation check, or gate-level simulation on the boot and reset tests. Key point 4 Some simulators also offer X-propagation modes that make RTL less optimistic.

What Interviewers Listen For (Staff)
A good staff answer spends effort where X does damage: control paths and reset. It names the cost of each check and who signs it off.

Wrong Altitude

"Run every test at gate level to catch X."

Gate-level runs are slow and add pessimistic X of their own. Target the boot and reset tests, and use formal or assertions for the rest.

Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 10.8 X-State Verification
- Lesson F5.5X-Propagation
- Lesson R2.2Reset: Assert, Release, and What RTL Cannot Show
What IfWhere X Values Come FromL1 JuniorL2 Mid-Level
Asked if they ask where the X comes from

Where does an X come from in RTL simulation in the first place?

Reveal the Model Answer

The usual sources are flops with no reset and memories never written. Others are two drivers fighting on a net, an index out of range, and a missing input connection. An X on a control signal is the dangerous kind, because optimism can hide it. An X in a data word guarded by a valid bit is often harmless.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The usual sources are flops with no reset and memories never written. Key point 2 Others are two drivers fighting on a net, an index out of range, and a missing input connection. Key point 3 An X on a control signal is the dangerous kind, because optimism can hide it. Key point 4 An X in a data word guarded by a valid bit is often harmless.

Missed Corner

"Two-state types such as bit remove the problem."

They remove the X in simulation, not the unknown power-up value in silicon. A missing reset is still a bug, now invisible.

Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. appendix C.6 Eliminating some of my X with 2-state data types
- Lesson R2.2Reset: Assert, Release, and What RTL Cannot Show
- Lesson R1.4Widths, Truncation and Sign
CompareX Optimism vs X PessimismL2 Mid-LevelL3 Senior
Compare X optimism and X pessimism. Which one hurts you at gate level?

Reveal the Model Answer

Optimism turns an unknown into a known value, so RTL looks better than silicon. Pessimism keeps X where silicon would have a real value, so simulation looks worse than silicon. Gate-level models are often pessimistic. An X that silicon would resolve can then spread and never clear, and the test fails for no real reason.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Optimism turns an unknown into a known value, so RTL looks better than silicon. Key point 2 Pessimism keeps X where silicon would have a real value, so simulation looks worse than silicon. Key point 3 Gate-level models are often pessimistic. Key point 4 An X that silicon would resolve can then spread and never clear, and the test fails for no real reason.

Half-Truth

"Gate-level X is always a real bug."

Gate models can be pessimistic: an X in a feedback loop may never clear in simulation even though silicon settles. Check before you fix.

Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. appendix C.4 A pessimistic X
- Lesson R2.2Reset: Assert, Release, and What RTL Cannot Show

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"An X on the select shows up as X on the output in RTL simulation."

Not for an if: X counts as false. The twin gets a clean 1010 from b with the select unknown.

Run It

The if form with sel = x, then the ?: form. Both synthesize to the same 4 mux cells.

RUNIcarus Verilog · in your browser

Edit the code, then run it

Expected: sel=x: y=1010 FAIL: if treated sel=x as false and gave a clean y=b; the X is hidden

module pick (input logic sel, input logic [3:0] a, b, output logic [3:0] y);
  always_comb if (sel) y = a; else y = b;
endmodule
module tb;
  logic sel; logic [3:0] a = 4'b1100, b = 4'b1010, y;
  pick dut (.sel(sel), .a(a), .b(b), .y(y));
  initial begin
    sel = 1'bx; #1;               // an unknown select, e.g. from an unreset flop
    $display("sel=x: y=%b", y);
    if (^y !== 1'bx) $display("FAIL: if treated sel=x as false and gave a clean y=b; the X is hidden");
  end
endmodule

See the Fix

module pick (input logic sel, input logic [3:0] a, b, output logic [3:0] y);
  always_comb y = sel ? a : b;
endmodule
module tb;
  logic sel; logic [3:0] a = 4'b1100, b = 4'b1010, y;
  pick dut (.sel(sel), .a(a), .b(b), .y(y));
  initial begin
    sel = 1'bx; #1;               // an unknown select, e.g. from an unreset flop
    $display("sel=x: y=%b", y);
    if (^y === 1'bx) $display("PASS: the unknown select shows as X where a and b differ");
  end
endmodule

Prints: sel=x: y=1xx0 PASS: the unknown select shows as X where a and b differ

Tool as Truth

"Verilator shows no X anywhere, so we have no X problems."

Verilator is a two-state simulator. Given sel = 1'bx, it printed 1010 for both the if and the ?: form, so it cannot show X at all.

Source Measured: both forms of the twin on Verilator, Verilator 5.052

Half-Truth

"Replace every if with ?: and X bugs are gone."

?: is less optimistic, but other constructs are optimistic too, and gate-level models can be pessimistic. No single coding change makes X behaviour match silicon.

Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. appendix C.4 A pessimistic X

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X Optimism in an If Statement

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