Interview Question · Concept
Half-Perimeter Wirelength
The Question
The interviewer asks
A net connects four pins at the corners of a 10 µm square. What is its half-perimeter wirelength, and how long is the shortest real wire?
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Reveal the Model Answer
HPWL is half the perimeter of the bounding box around a net's pins, here 10 + 10 = 20 µm. The shortest rectilinear tree that joins four corners must run three sides of the square, 30 µm. HPWL is exact for two- and three-pin nets without obstacles, and a lower bound for larger nets. That is why placers use it as a fast estimate, not as the routed length.
- HPWL (µm)
- overflow
- Iteration 0HPWL (µm) = 1270 · overflow = 0.9783
The starting point: every net short, HPWL 1270 µm, overflow 0.9783.
- Iteration 40HPWL (µm) = 924.8 · overflow = 0.9645
The density penalty is still weak, and the wirelength term pulls nets even shorter: 925 µm.
- Iteration 250HPWL (µm) = 3339 · overflow = 0.4921
The penalty has grown. Cells flow outward, overflow passes 0.4921, and HPWL climbs to 3339 µm.
- Iteration 361HPWL (µm) = 4142 · overflow = 0.0991
Overflow 0.0991 is below the stop value of 0.1, so the placer stops with 4142 µm of wire.
Read the plot as a table
| Iteration | HPWL (µm) | overflow |
|---|---|---|
| 0 | 1270 | 0.9783 |
| 40 | 924.8 | 0.9645 |
| 50 | 925.6 | 0.966 |
| 100 | 935.2 | 0.9589 |
| 150 | 1199 | 0.928 |
| 200 | 2345 | 0.7335 |
| 250 | 3339 | 0.4921 |
| 300 | 3898 | 0.2466 |
| 350 | 4107 | 0.1219 |
| 361 | 4142 | 0.0991 |
The placer's own log on lesson L4.1's MAC. HPWL is the wirelength it reports at every step, because it is fast to compute.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer draws the bounding box and gets 20 µm. It then draws the 30 µm Steiner tree, which is the shortest real wire that joins the four corners.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains why placers optimise a smooth stand-in for wirelength, and when HPWL is too low. It checks the routed wirelength and the congestion before it trusts the number.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompareScale It
- Half-Perimeter Wirelength
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WhyWhy HPWL Is Only a Lower BoundL1 Junior
Why is HPWL exact for a three-pin net but only a lower bound for a five-pin net?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Any tree that reaches every pin must span the bounding box once horizontally and once vertically. So it is at least the half perimeter. With three pins one trunk and one branch always achieve that. With more pins the tree needs extra branches inside the box, as the four-corner square shows, so real wire exceeds the bound.
Self-Check
Tick each key point you covered in your answer.
-
ComparePlaced HPWL vs Routed WirelengthL1 JuniorL2 Mid-Level
Compare placed HPWL with the wirelength the router reports. Why can they move in opposite directions?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
HPWL sums pin boxes and ignores how crowded the routing is. The router has to share tracks, so in a dense cluster it detours and uses more wire. In lesson L4.2 raising the target density from 0.6 to 0.95 cut HPWL from about 6244 to 5119 µm while routed wire rose from 18326 to 18719 µm.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve L4.3.1: Recover Wirelength After LegalizationSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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What IfWhat a Global Placer OptimisesL1 JuniorL2 Mid-Level
What if you ran global placement with wirelength as the only goal?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Every connected cell would pile into one spot, which is short wire and impossible to build. An analytic placer minimises a smooth wirelength plus a density penalty whose weight grows each iteration. It stops when overflow falls low enough. Overflow is the share of cell area above the target density. In lesson L4.1 the run stopped at iteration 361 with overflow 0.099.
Self-Check
Tick each key point you covered in your answer.
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Scale ItTarget Density and CongestionL1 JuniorL2 Mid-Level
What does the placer's target density control, and how does it relate to routing congestion?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Target density is the local fill the placer aims for; it must sit above the overall utilization or cells cannot spread. A higher target clusters connected cells, which shortens wires but concentrates routing demand on the clusters. Congestion is that demand compared with the tracks available in each routing tile. So the global router's overflow map, not HPWL, says whether the density choice was too aggressive.
From Target Density to the Overflow MapArrows show what each choice drives. Read the diagram as text
- Core utilization: One number for the whole core
- Target density: Local fill the placer aims for
- Tighter clusters: Shorter wires
- Routing demand per tile: Wires that must pass through
- Tracks per tile: Less the router's reserve
- Overflow map: Demand above the tracks
- Core utilization → Target density: sets the minimum
- Target density → Tighter clusters: higher target
- Tighter clusters → Routing demand per tile: concentrates
- Routing demand per tile → Overflow map
- Tracks per tile → Overflow map
The overflow map, not HPWL, says whether the density was too aggressive.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer keeps target density apart from utilization. It says a higher density gives shorter wires but raises the risk of congestion.
What Interviewers Listen For (Senior)
A good senior answer reads the overflow report for each layer. It tries routability-driven placement or a lower density before it changes the floorplan. It re-checks timing after each fix.
Missed Corner
"Set target density equal to the utilization so cells spread evenly."
The placer needs room above the average fill to move cells. If the target is below the free-area minimum, the tool raises it with a warning.
Source ASIC Point lesson L3.1 (GPL-0302 measured)
Half-Truth
"Zero global-route overflow means routing will be clean."
Global routing plans coarse resources per tile. Pin access, via rules and local crowding are decided only in detailed routing, which can still fail.
Source ASIC Point lessons L6.1 and L6.2
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CompareTarget Density vs UtilizationL1 Junior
Compare core utilization with the placer's target density.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Utilization is one number for the whole core: cell area over core area, fixed by the floorplan. Target density is a local goal the placer pushes every region toward, so it controls how tightly cells cluster within that core. A 40 % core can be placed at density 0.6 or 0.95, with very different wire and congestion.
Self-Check
Tick each key point you covered in your answer.
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WhyWhy the Router Holds Tracks BackL1 JuniorL2 Mid-Level
Why does the global router count fewer tracks than the layer really has?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The platform reduces each layer's capacity, by 20 % on sky130 here. This leaves room for pin access, vias and detours that the coarse model cannot see. Overflow is measured against that reduced capacity. Changing the adjustment changes the plan's resources, not the physical tracks, so it can hide congestion rather than fix it.
Self-Check
Tick each key point you covered in your answer.
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What IfRelieving Placement CongestionL2 Mid-LevelL3 Senior
Asked if they see overflow on the map
The global-route map shows overflow in one corner of the block. Which remedies do you try, in what order?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Start cheap and local: lower the target density or turn on routability-driven placement, which inflates cells in crowded regions. Then look at the cause, such as a pin cluster, a wide multiplexer or a macro channel. Fix that cause with a pin plan or floorplan change. Lower utilization is the expensive last resort. Re-check timing after each step, because spreading costs wire.
Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve L6.3.1: Give the Crossbar Pins RoomSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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WhyWhy Local Congestion Fixes Come FirstL2 Mid-Level
Why try routability-driven placement before lowering the utilization of the whole block?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Routability-driven placement adds room only where the router predicts overflow. Lower utilization grows the whole block, so area and wire grow everywhere. The local fix keeps the dense, short-wired regions that had no problem. So it is the cheaper first step.
Self-Check
Tick each key point you covered in your answer.
Wrong Altitude
"Lower utilization fixes congestion, so start there."
It is the most expensive remedy, because it changes the block size and the parent floorplan. Try the local fixes first.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"HPWL is the routed wirelength."
It is a bound from the pin box. Nets with more than three pins, detours around blockages and layer changes all make real wire longer.
Source ASIC Point lesson L4.1 (Kahng, Lienig, Markov, Hu, VLSI Physical Design, ch. 4 slides, as cited)
Half-Truth
"Lower HPWL always means a better placement."
A placer can pack cells tightly to cut HPWL and create routing hot spots. In lesson L4.2 a higher target density cut placed HPWL yet raised the routed wirelength.
Source ASIC Point lesson L4.2 (measured)