Interview Question · Code Writing

Writing Input and Output Delays

L1 JuniorL2 Mid-Levelstaconstraintssdc

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The interviewer asks

Write the SDC that times the ports of a block clocked at 5 ns. Inputs arrive 4 ns after the edge. The outside needs outputs 1 ns before the next edge.

Reveal the Model Answer

Declare the clock, then set_input_delay 4 -clock clk on the data inputs and set_output_delay 1 -clock clk on the outputs. Add a -min value for hold on each side. Add set_driving_cell on the inputs and set_load on the outputs, so the port nets have real delay and slew. Then run check_setup to see that no port is left untimed.

One Path Through Three BlocksArrows are data. The two outer halves are what the input and output delays stand for.

Input delay
set_input_delay is the time from the clock edge to the signal's arrival at the port: the outside flop's clock-to-Q plus the outside logic.
Inside the block
The block's own run times the rest, from the port to its registers, against the next edge.
Output delay
set_output_delay is how much of the cycle the outside still needs after the port: its logic plus its flop's setup.

Read the diagram as text

Controller flop: launches on clk
en port: arrives input delay after the edge
MAC registers: capture, then launch
acc port: needed output delay before the edge
Next block's flop: captures on clk

Controller flop → en port: input delay
en port → MAC registers: block logic
MAC registers → acc port: clock-to-Q
acc port → Next block's flop: output delay

Both delays are measured from the same clock edge the block uses.

Timing pathEn into the MAC, with the Controller's Delayset_input_delay 4 puts the arrival at the port 4 ns after the edge; a buf_4 drives the port.

en → _827_setup check, latest arrival4 cells

Clock latency
Cell delay
Input delay
Setup time

Outside the block
The controller's flop and logic take 4 ns, written as the input delay. The buf_4 that drives en then charges 0.1868 pF on 69 pins: 0.3589 ns.
Inside the MAC
The MAC's own gates add 0.9227 ns, starting at the slow slew the port left.
Violated
Arrival 5.2816 ns, required 4.8985 ns: slack -0.3830 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 5.0000 ns, latency 0.0000 ns, library setup time −0.1015 ns.

Arrival 5.2816 ns, required 4.8985 ns, slack −0.3830 ns (violated).

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
	`en` → `_738_/B1`	wire en	rise	0.0000	4.3589	0.5105
1	`_738_/B1` → `_738_/Y`	o21ai_0	fall	0.1989	4.5577	0.1542
	`_738_/Y` → `_740_/B1`	wire _103_	fall	0.0000	4.5577	0.1542
2	`_740_/B1` → `_740_/Y`	a211oi_1	rise	0.4381	4.9959	0.4445
	`_740_/Y` → `_742_/C`	wire _105_	rise	0.0000	4.9959	0.4445
3	`_742_/C` → `_742_/Y`	nand3_1	fall	0.1474	5.1433	0.1059
	`_742_/Y` → `_748_/B`	wire _107_	fall	0.0000	5.1433	0.1059
4	`_748_/B` → `_748_/Y`	xnor2_1	fall	0.1383	5.2816	0.0445
	`_748_/Y` → `_827_/D`	wire _048_	fall	0.0000	5.2816	0.0445

The report

Startpoint: en (input port clocked by clk)
Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
Path Group: in2reg
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                              4.0000    4.0000 ^ input external delay
    69    0.1868    0.5105    0.3589    4.3589 ^ en (in)
                                                 en (net)
                    0.5105    0.0000    4.3589 ^ _738_/B1 (sky130_fd_sc_hd__o21ai_0)
     2    0.0044    0.1542    0.1989    4.5577 v _738_/Y (sky130_fd_sc_hd__o21ai_0)
                                                 _103_ (net)
                    0.1542    0.0000    4.5577 v _740_/B1 (sky130_fd_sc_hd__a211oi_1)
     4    0.0119    0.4445    0.4381    4.9959 ^ _740_/Y (sky130_fd_sc_hd__a211oi_1)
                                                 _105_ (net)
                    0.4445    0.0000    4.9959 ^ _742_/C (sky130_fd_sc_hd__nand3_1)
     1    0.0045    0.1059    0.1474    5.1433 v _742_/Y (sky130_fd_sc_hd__nand3_1)
                                                 _107_ (net)
                    0.1059    0.0000    5.1433 v _748_/B (sky130_fd_sc_hd__xnor2_1)
     1    0.0019    0.0445    0.1383    5.2816 v _748_/Y (sky130_fd_sc_hd__xnor2_1)
                                                 _048_ (net)
                    0.0445    0.0000    5.2816 v _827_/D (sky130_fd_sc_hd__dfrtp_1)
                                        5.2816   data arrival time

                    0.1000    5.0000    5.0000   clock clk (rise edge)
                              0.0000    5.0000   clock network delay (ideal)
                              0.0000    5.0000   clock reconvergence pessimism
                                        5.0000 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
                             -0.1015    4.8985   library setup time
                                        4.8985   data required time
-------------------------------------------------------------------------------------
                                        4.8985   data required time
                                       -5.2816   data arrival time
-------------------------------------------------------------------------------------
                                       -0.3830   slack (VIOLATED)

An input path of lesson L2.7's MAC with the controller's input delay. The arrival starts late, at the input delay.

The SDC of lesson L2.7 (the run uses it)

create_clock -name clk -period 5 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_input_delay 4 -clock clk [delete_from_list [all_inputs] [get_ports clk]]
set_output_delay -max 1 -clock clk [all_outputs]
set_output_delay -min -0.2 -clock clk [all_outputs]
set_driving_cell -lib_cell sky130_fd_sc_hd__buf_4 -pin X [delete_from_list [all_inputs] [get_ports clk]]
set_load 0.01 [all_outputs]
group_path -name in2reg -from [all_inputs]
group_path -name reg2out -to [all_outputs]

Self-Check

Tick each key point you covered in your answer.

Key point 1 Declare the clock, then set_input_delay 4 -clock clk on the data inputs and set_output_delay 1 -clock clk on the outputs. Key point 2 Add a -min value for hold on each side. Key point 3 Add set_driving_cell on the inputs and set_load on the outputs, so the port nets have real delay and slew. Key point 4 Then run check_setup to see that no port is left untimed.

What Interviewers Listen For (Junior)

A good junior answer writes the clock and the input and output delays with -clock. It explains what each number means.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompare

Writing Input and Output Delays
WhyA Negative Minimum Output DelayL2 Mid-Level
Why is the minimum output delay often negative, as in set_output_delay -min -0.2?
2:30

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Reveal the Model Answer

The output delay models the receiving flop outside the block. For hold, the receiver needs the data to stay stable for its hold time after the edge. That shows up as a negative minimum output delay. In lesson L2.7 a min output delay of -0.2 ns made the output hold check require 0.2 ns, met with 0.2121 ns of slack.

Timing pathHold at an Acc Portset_output_delay -min -0.2: the required time moves to +0.2 ns.

_827_ → acc[19]hold check, earliest arrival1 cell
Clock latency
Cell delay
Hold time
Hold after the edge
Required after 0.2000 ns: the negative minimum delay is a positive hold time outside.
Met
The flop's clock-to-Q keeps the old value until 0.4121 ns: slack 0.2121 ns.

Read the path as a table

Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 0.0000 ns, latency 0.0000 ns, library hold time 0.2000 ns.

Arrival 0.4121 ns, required 0.2000 ns, slack 0.2121 ns (met).

Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns)
1 _827_/CLK → _827_/Q dfrtp_1 rise 0.4121 0.4121 0.1416
_827_/Q → acc[19] wire acc[19] rise 0.0000 0.4121 0.1416

The report
Startpoint: _827_ (rising edge-triggered flip-flop clocked by clk) Endpoint: acc[19] (output port clocked by clk) Path Group: reg2out Path Type: min Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.1000 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.1000 0.0000 0.0000 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1) 2 0.0147 0.1416 0.4121 0.4121 ^ _827_/Q (sky130_fd_sc_hd__dfrtp_1) acc[19] (net) 0.1416 0.0000 0.4121 ^ acc[19] (out) 0.4121 data arrival time 0.1000 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.0000 0.0000 clock reconvergence pessimism 0.2000 0.2000 output external delay 0.2000 data required time ------------------------------------------------------------------------------------- 0.2000 data required time -0.4121 data arrival time ------------------------------------------------------------------------------------- 0.2121 slack (MET)

Hold at an output port with set_output_delay -min -0.2: the check requires 0.2 ns and passes with 0.2121 ns.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The output delay models the receiving flop outside the block. Key point 2 For hold, the receiver needs the data to stay stable for its hold time after the edge. Key point 3 That shows up as a negative minimum output delay. Key point 4 In lesson L2.7 a min output delay of -0.2 ns made the output hold check require 0.2 ns, met with 0.2121 ns of slack.
- Lesson L2.7Input and Output Delays
Prove ItSolve L2.7.1: Budget Both Sides of the BlockSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem L2.7.1
What IfConstraining a Divided ClockL1 JuniorL2 Mid-Level
Asked if the block has a divided clock

A flop divides the main clock by two to clock half the block. How do you constrain it?
2:30

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Reveal the Model Answer

Declare it with create_generated_clock -source on the master clock pin and -divide_by 2 at the divider's output. Then the tool keeps its phase relation to the master. With only the master clock, check_setup reports the divided flops as unclocked. A plain create_clock on the divider output would lose the divider's latency, which the lesson measured as 0 instead of 0.3425 ns.

div2: The Clock Stops at the DividerArrows are signals. clk reaches dv and ra; the divided net clkd clocks rb and rc.

The clock stops at dv
The tool follows clk to the CLK pins of dv and ra. It does not cross dv.
Declare the divided clock
create_generated_clock -divide_by 2 -source [get_ports clk] on dv/Q names a 2 ns clock tied to clk.
Crossings are timed
Now ra → rb is a path from clk to clkd, checked with edges of both clocks.

Read the diagram as text
clk port: create_clock, 1 ns
dv (dfxtp_1): toggles every edge
ra (dfxtp_1): on clk
clkd net: create_generated_clock
rb, rc (dfxtp_1): on clkd
clk port → dv (dfxtp_1): clock
clk port → ra (dfxtp_1): clock
dv (dfxtp_1) → clkd net: Q
clkd net → rb, rc (dfxtp_1): clock
ra (dfxtp_1) → rb, rc (dfxtp_1): data

A generated clock keeps its master, so the tool knows where its edges fall relative to clk.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Declare it with create_generated_clock -source on the master clock pin and -divide_by 2 at the divider's output. Key point 2 Then the tool keeps its phase relation to the master. Key point 3 With only the master clock, check_setup reports the divided flops as unclocked. Key point 4 A plain create_clock on the divider output would lose the divider's latency, which the lesson measured as 0 instead of 0.3425 ns.
- Lesson L2.6Clocks in SDC
CompareReal Clock vs Virtual Clock for I/OL2 Mid-Level
Compare referencing I/O delays to the block's real clock with referencing them to a virtual clock.
2:30

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Reveal the Model Answer

A virtual clock has no source pin in the block; it stands for the clock at the external device. Referenced to the real clock, I/O paths shift when CTS makes that clock propagated, by about the insertion delay. A virtual clock with an agreed source latency keeps the external timing fixed. So the I/O budget means the same before and after CTS.

Timing pathThe Input Path After CTS, with the Virtual-Clock BudgetI/O delays on vclk, which has a source latency of 0.3 ns.

en → _797_hold check, earliest arrival1 cell
Clock latency
Cell delay
Wire delay
Input delay
Hold time
The outside edge, late too
vclk reaches the external flop at 0.3000 ns.
The tree
The capture flop still sees the edge at 0.3116 ns.
Met
Hold slack 0.1742 ns. The output path gets its setup back too: 3.5505 ns.

Read the path as a table

Launch: vclk rise edge at 0.0000 ns, clock latency 0.3000 ns. Capture: clk rise edge at 0.0000 ns, latency 0.3116 ns, library hold time −0.0279 ns.

Arrival 0.4579 ns, required 0.2837 ns, slack 0.1742 ns (met).

Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns)
en → _700_/A1 wire en rise 0.0121 0.4121 0.0243
1 _700_/A1 → _700_/Y a21oi_1 fall 0.0457 0.4579 0.0328
_700_/Y → _797_/D wire _006_ fall 0.0001 0.4579 0.0328

The report
Startpoint: en (input port clocked by vclk) Endpoint: _797_ (rising edge-triggered flip-flop clocked by clk) Path Group: in2reg Path Type: min Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock vclk (rise edge) 0.3000 0.3000 clock network delay (propagated) 0.1000 0.4000 ^ input external delay 69 0.2810 0.0000 0.0000 0.4000 ^ en (in) en (net) 0.0243 0.0121 0.4121 ^ _700_/A1 (sky130_fd_sc_hd__a21oi_1) 1 0.0026 0.0328 0.0457 0.4579 v _700_/Y (sky130_fd_sc_hd__a21oi_1) _006_ (net) 0.0328 0.0001 0.4579 v _797_/D (sky130_fd_sc_hd__dfrtp_1) 0.4579 data arrival time 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0254 0.0000 0.0000 0.0000 ^ clk (in) clk (net) 0.0004 0.0002 0.0002 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 4 0.0309 0.0676 0.1297 0.1299 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_8) clknet_0_clk (net) 0.0676 0.0007 0.1306 ^ clkbuf_2_1__f_clk/A (sky130_fd_sc_hd__clkbuf_8) 14 0.0526 0.1017 0.1798 0.3103 ^ clkbuf_2_1__f_clk/X (sky130_fd_sc_hd__clkbuf_8) clknet_2_1__leaf_clk (net) 0.1017 0.0012 0.3116 ^ _797_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.0000 0.3116 clock reconvergence pessimism -0.0279 0.2837 library hold time 0.2837 data required time ------------------------------------------------------------------------------------- 0.2837 data required time -0.4579 data arrival time ------------------------------------------------------------------------------------- 0.1742 slack (MET)

The input path after CTS with a virtual clock and an agreed source latency: hold passes with 0.1742 ns.

Self-Check
Tick each key point you covered in your answer.
Key point 1 A virtual clock has no source pin in the block; it stands for the clock at the external device. Key point 2 Referenced to the real clock, I/O paths shift when CTS makes that clock propagated, by about the insertion delay. Key point 3 A virtual clock with an agreed source latency keeps the external timing fixed. Key point 4 So the I/O budget means the same before and after CTS.
WhyWhy I/O Paths Shift After CTSL2 Mid-Level
Why do inputs gain setup and lose hold after CTS, when their delays are referenced to the real clock?

Reveal the Model Answer

After CTS the capture flop sees the clock later, by the insertion delay. The input delay is still counted from the edge at the clock port. So the data has extra time for setup, and hold gets harder by about the same amount. Outputs move the other way.

Self-Check
Tick each key point you covered in your answer.
Key point 1 After CTS the capture flop sees the clock later, by the insertion delay. Key point 2 The input delay is still counted from the edge at the clock port. Key point 3 So the data has extra time for setup, and hold gets harder by about the same amount. Key point 4 Outputs move the other way.

Missed Corner

"CTS changes only internal paths."

It also moves the clock at every boundary flop. I/O paths referenced to the real clock shift by the insertion delay.

Source Lesson L5.3 key points
- Lesson L5.3From Ideal to Propagated Clocks
- Lesson L2.7Input and Output Delays

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
1	`_827_/CLK` → `_827_/Q`	dfrtp_1	rise	0.4121	0.4121	0.1416
	`_827_/Q` → `acc[19]`	wire acc[19]	rise	0.0000	0.4121	0.1416

Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
	`en` → `_700_/A1`	wire en	rise	0.0121	0.4121	0.0243
1	`_700_/A1` → `_700_/Y`	a21oi_1	fall	0.0457	0.4579	0.0328
	`_700_/Y` → `_797_/D`	wire _006_	fall	0.0001	0.4579	0.0328

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Missed Corner

"The driving cell is a detail; the input delay is what matters."

Without it the input port has no drive delay. The en net feeds 69 pins: with a buf_4 driving it the path fails by 0.3830 ns, without one it passes by 0.1294 ns.

Run It

The MAC from lesson L2.7 with its I/O constraints, but no driving cell on the inputs.

create_clock -name clk -period 5 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_input_delay 4 -clock clk [delete_from_list [all_inputs] [get_ports clk]]
set_output_delay -max 1 -clock clk [all_outputs]
set_output_delay -min -0.2 -clock clk [all_outputs]
set_load 0.01 [all_outputs]
group_path -name in2reg -from [all_inputs]
group_path -name reg2out -to [all_outputs]

Prints: 0.1294 slack (MET)

See the Fix

create_clock -name clk -period 5 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_input_delay 4 -clock clk [delete_from_list [all_inputs] [get_ports clk]]
set_output_delay -max 1 -clock clk [all_outputs]
set_output_delay -min -0.2 -clock clk [all_outputs]
set_driving_cell -lib_cell sky130_fd_sc_hd__buf_4 -pin X [delete_from_list [all_inputs] [get_ports clk]]
set_load 0.01 [all_outputs]
group_path -name in2reg -from [all_inputs]
group_path -name reg2out -to [all_outputs]

Prints: -0.3830 slack (VIOLATED) 3.5429 slack (MET)

Half-Truth

"A block that passes alone will pass in the chip."

Unconstrained I/O is not timed at all, and loose input delays hide the real budget. The block must be timed against agreed budgets for each port.

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Writing Input and Output Delays

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