Interview Question · Debug
The Write That Happened on IDLE
The Question
The interviewer asks
A register reads back correctly right after a write, but two cycles later the same read returns 0. Between the reads the manager drove IDLE and left the last address and control on the bus. What is the bug?
Illustrative register-test excerpt
WRITE A=1 -> OKAY
READ A -> 1
IDLE: HADDR=A, HWRITE=1, HWDATA=0
READ A -> 0 (expected 1)You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The register block takes address phases without checking HTRANS. IDLE and BUSY must get a zero-wait OKAY and be ignored. But the manager may leave the last write's HADDR and HWRITE on the bus. A block that decodes only HSEL, HWRITE and HADDR treats each IDLE as another write. It stores whatever HWDATA holds. Take a write only when HSEL and HREADY are high and HTRANS is NONSEQ or SEQ.
A row lights when its word is written; beat_a and beat_m are the address and lanes of the data phase that ends at the edge.
- Cycle 4
NONSEQ: the first beat of an INCR4 burst at 0x200. Its address and control have nothing to do with what came before.
- Cycle 5
SEQ at 0x204, the previous address plus four bytes, with identical control. Beat 0's data, b0, lands in the first row.
- Cycle 6
BUSY: the manager cannot send beat 2 yet. The address already shows 0x208, the next beat. Beat 1's data still lands, because its data phase is this cycle.
- Cycle 7
SEQ at 0x208: beat 2 goes out. Nothing lands in this cycle: the BUSY had no data phase, and the memory answered it with a zero-wait OKAY.
- Cycle 9
IDLE: no transfer. Address and control keep their last values, and the memory must ignore them. Beat 3's data lands.
- Cycle 11
The single read of 0x208, a NONSEQ with burst type SINGLE, returns b2.
Measured. In the IDLE cycles the last address and HWRITE stay on the bus. A correct memory writes nothing then.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer finds the missing HTRANS check. It knows IDLE and BUSY must be ignored and answered with a zero-wait OKAY.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains why the read-back right after the write still passed. It adds a test with idle gaps and a stale HWRITE, and notes that a protocol checker cannot see this bug.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItCompareScale It
- The Write That Happened on IDLE
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CompareIDLE Against BUSYL1 Junior
IDLE and BUSY both move no data. What is the difference, and what must the subordinate do for each?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
IDLE means the manager wants no transfer. BUSY means a burst is continuing, but its next beat is not ready yet. Its address and control already describe that next beat. The subordinate answers both the same way: a zero-wait OKAY and no action.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says who issues each one: IDLE when no transfer is wanted, BUSY inside a burst. It knows both get a zero-wait OKAY.
What Interviewers Listen For (Mid-Level)
A good mid-level answer knows BUSY may not end a fixed-length burst or follow a SINGLE. It knows an INCR burst may end after BUSY with IDLE or NONSEQ.
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WhyBUSY and the End of a BurstL2 Mid-Level
Why does a BUSY cycle carry the address of the next beat, and which bursts may end with BUSY?
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Reveal the Model Answer
It keeps the burst continuous. When the manager is ready, it turns BUSY into SEQ with the same address. So the subordinate can keep prefetching. Only an undefined-length INCR may end after BUSY, followed by IDLE or NONSEQ. Fixed-length INCR4/8/16 and WRAP4/8/16 must end with a SEQ beat, and BUSY may never follow a SINGLE.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer states the rules for how each burst type may end, exactly.
What Interviewers Listen For (Senior)
A good senior answer writes those rules as checker properties. It makes sure stimulus puts BUSY inside every burst type, so the rules are really tested.
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Break ItWhat the AHB Checker MissesL2 Mid-LevelL3 Senior
Would an AHB protocol checker have caught the write-on-IDLE bug? What does, and how do you split the work between checker and scoreboard?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
No. Every wire was legal, because the manager may leave the address on the bus during IDLE. Only the data shows the bug. A scoreboard or register model that reads back after idle gaps catches it. Assertions own the wire rules (holds, two-cycle ERROR, SEQ addresses, 1 KB crossings). The scoreboard owns subordinate behaviour (data taken in the wrong phase, lanes HSIZE did not select, actions on IDLE).
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says the wire checker cannot see this bug. It names the scoreboard check that does.
What Interviewers Listen For (Senior)
A good senior answer states the split as a method: assertions own the wire rules and the scoreboard owns subordinate behaviour. It adds coverage for idle gaps with stale controls, narrow writes and back-to-back reads across subordinates.
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Scale ItInterconnect Bugs That Pass Block TestsL2 Mid-LevelL3 Senior
Every subordinate passes its own block-level tests, yet the SoC sometimes reads wrong data. Which interconnect bugs slip past block tests, and what traffic exposes them?
log Illustrative integration-test excerpt Subordinate A unit tests: pass Subordinate B unit tests: pass SoC read A, then read B with wait states: read B returned data expected from A; response OKAY2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
These bugs need two subordinates at once. A mux select on the wrong phase shows only on back-to-back accesses to different subordinates. A HREADY fan-in that forwards the wrong HREADYOUT shows only when one subordinate waits while another is addressed. A region off-by-one shows only at a 1 KB edge, and a one-cycle default-subordinate error only on unmapped accesses. Expose them with back-to-back cross-subordinate traffic, random waits and address sweeps at every region boundary.
Each Read Returns the Read Before ItFour reads, m0, m1, m0, m1, with the multiplexor keyed by the address-phase select. Watch HRDATA arrive one transfer late. All cyclesdata_sel is the subordinate in the data phase: the one the multiplexor should listen to.
- Cycle 0
The read of 0x0100 is in its address phase. The decoder selects m0.
- Cycle 1
Its data phase ends here, and m0 is answering. But the address phase now names 0x1100, so the broken multiplexor passes m1's HRDATA: 00000000.
- Cycle 2
The read of 0x1100 ends. The address phase names m0 again, and the multiplexor hands over m0's word, 0a0a0a0a.
- Cycle 3
The second read of 0x0100 gets m1's 1b1b1b1b. Every read so far has the data of the one before it.
- Cycle 4
Only the last read comes back right, because no new address phase follows it.
Measured. A multiplexor keyed by the address-phase select returns each read the data of the read before it. No wire rule fires.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names the cases that need two subordinates at once. It names the traffic that reaches them.
What Interviewers Listen For (Senior)
A good senior answer writes coverage for them: previous subordinate crossed with current subordinate and wait state, plus bins at region edges. This proves random traffic really hits them.
- Cycle 0
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Prove ItSolve P4.12.3: The Read That Returned Its Neighbour's DataSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Prove ItSolve P4.3.1: The Write That Happened on IDLESimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
IDLE carries no transfer, so decoding HADDR and HWRITE without HTRANS is harmless.
IDLE carries no transfer, but HADDR and HWRITE still hold values. A manager may leave the last write's values on the bus, as the twin below does. The block that ignores HTRANS writes 00000000 over 11223344.
Run It
FAIL ignores_htrans: register 0x10 holds 00000000 PASS checks_htrans: register 0x10 holds 11223344Spec Misquote
HSEL is enough; the decoder drops HSEL on IDLE cycles.
HSELx may be high or low for IDLE transfers. Only a non-IDLE transfer requires it. A decoder is free to keep HSEL high on IDLE.
Source AMBA AHB Protocol Specification IHI 0033C §2.4 Decoder signals
Misconception
BUSY is the subordinate telling the manager to wait.
BUSY comes from the manager: it pauses inside a burst and already shows the next beat's address. A subordinate makes the manager wait with HREADYOUT low.
Source AMBA AHB Protocol Specification IHI 0033C §3.2 Transfer types